dspic33fj128gp204 Microchip Technology Inc., dspic33fj128gp204 Datasheet - Page 83

• Manufacturer Part Number: dspic33fj128gp204
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

FIGURE 6-3:
6.3
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse-width will generate a Reset. Refer
to Section 30.0 “Electrical Characteristics” for
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.3.0.1
Many systems have external supervisory circuits that
generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.3.0.2
When using the internal power supervisory circuit to
Reset the device, the external reset pin (MCLR) should
be tied directly or resistively to V
MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a spe-
cial Reset state. This Reset state will not re-initialize the
clock. The clock source in effect prior to the RESET
instruction will remain. SYSRST is released at the next
instruction cycle, and the reset vector fetch will com-
mence.
© 2009 Microchip Technology Inc.
SYSRST
SYSRST
SYSRST
External Reset (EXTR)
Software RESET Instruction (SWR)
V
V
V
DD
DD
DD
EXTERNAL SUPERVISORY CIRCUIT
INTERNAL SUPERVISORY CIRCUIT
V
DD
dips before PWRT expires
BROWN-OUT SITUATIONS
DD
. In this case, the
Preliminary
T
BOR
+ T
T
T
PWRT
BOR
BOR
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate
the software Reset.
6.5
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control (RCON<4>) register is set to indicate
the
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
6.6
If a lower-priority hard trap occurs while a higher-prior-
ity trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on trap conflict Resets.
+ T
+ T
PWRT
PWRT
Watchdog
Watchdog Time-out Reset (WDTO)
Trap Conflict Reset
Reset.
Refer
V
V
V
BOR
BOR
BOR
DS70292C-page 81
to
Section 27.4