at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 125

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

19.4.1.2
19.4.2
19.4.2.1
19.4.2.2
19.4.2.3
19.4.3
6384B–ATARM–15-Dec-08
Round-Robin Arbitration
Fixed Priority Arbitration
Slot Cycle Limit Arbitration
Round-Robin Arbitration without Default Master
Round-Robin Arbitration with Last Access Master
Round-Robin Arbitration with Fixed Default Master
The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a
very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter
reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or
word transfer.
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave in a round-robin manner. If two or more master’s requests arise at the same
time, the master with the lowest number is first serviced then the others are serviced in a round-
robin manner.
There are three round-robin algorithms implemented:
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch
requests from different masters to the same slave in a pure round-robin manner. At the end of
the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency cycle for the first access of a burst. Arbitration without
default master can be used for masters that perform significant bursts.
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to
remove the one latency cycle for the last master that accessed the slave. At the end of the cur-
rent transfer, if no other master request is pending, the slave remains connected to the last
master that performs the access. Other non privileged masters still get one latency cycle if they
want to access the same slave. This technique can be used for masters that mainly perform sin-
gle accesses.
This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one
latency cycle for the fixed default master per slave. At the end of the current access, the slave
remains connected to its fixed default master. Requests attempted by this fixed default master
do not cause any latency whereas other non privileged masters get one latency cycle. This tech-
nique can be used for masters that mainly perform single accesses.
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixed priority defined by the user. If two or more master’s requests
are active at the same time, the master with the highest priority number is serviced first. If two or
more master’s requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (MATRIX_PRAS and MATRIX_PRBS).
• Round-Robin arbitration without default master
• Round-Robin arbitration with last access master
• Round-Robin arbitration with fixed default master
AT91SAM9G20 Preliminary
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