at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 181

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 21-26. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
21.11 External Wait
21.11.1
6384B–ATARM–15-Dec-08
write2 controlling signal
read1 controlling signal
NBS0, NBS1,
NBS2, NBS3,
A0, A1
Restriction
D[31:0]
A[25:2]
(NWE)
(NRD)
MCK
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be
set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00”
(disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT
signal delays the read or write operation in regards to the read or write controlling signal,
depending on the read and write modes of the corresponding chip select.
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle
for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page
Mode
page
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
TDF_CYCLES = 5
187).
(“Asynchronous Page Mode” on page
read1 cycle
read1 hold = 1
Read to Write
Wait State
TDF_CYCLES = 5
AT91SAM9G20 Preliminary
4 TDF WAIT STATES
190), or in Slow Clock Mode
write2 setup = 1
(optimization disabled)
(“Slow Clock Mode” on
TDF_MODE = 0
write2 cycle
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