at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 799

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

44.2.4
44.2.4.1
44.2.5
44.2.5.1
44.2.5.2
44.2.6
44.2.6.1
6384B–ATARM–15-Dec-08
Static Memory Controller (SMC)
Serial Peripheral Interface (SPI)
Serial Synchronous Controller (SSC)
SMC: Chip Select Parameters Modification
SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0
SPI: Baudrate set to 1
SSC: Unexpected RK clock cycle when RK outputs a clock during data transfer
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse,
Cycle, Mode) if accesses are performed on this CS during the modification.
For example, the modification of the Chip Select 0 (CS0) parameters, while fetching the code
from a memory connected on this CS0, may lead to unpredictable behavior.
The code used to modify the parameters of an SMC Chip Select can be executed from the inter-
nal RAM or from a memory connected to another Chip Select
If the SPI is used in the following configuration:
then an additional pulse will be generated on output PSCK during the second transfer.
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if CPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
When Baudrate is set to 1 (i.e., when serial clock frequency equals the system clock frequency),
and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case
9,11,13 or 15), an additional pulse is generated on output SPCK. No error occurs if BITS field
equals 8,10,12,14 or 16 and Baudrate = 1.
None.
When the SSC receiver is used in the following configuration:
then, at the end of the data, the RK pin is set in high impedance which may be interpreted as an
unexpected clock cycle.
• master mode
• CPOL =1 and NCPHA = 0
• multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• transmit with the slowest chip select and then with the fastest one
• the internal clock divider is used (CKS =0 and DIV different from 0),
• RK pin set as output and provides the clock during data transfer (CKO=2)
• data sampled on RK falling edge (CKI =0)
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR not equal to 1
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9G20 Preliminary
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