at91sam9g20-cu ATMEL Corporation, at91sam9g20-cu Datasheet - Page 14

• Manufacturer Part Number: at91sam9g20-cu
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

7.2
7.2.1
14
Bus Matrix
AT91SAM9G20 Preliminary
Matrix Masters
The Bus Matrix of the AT91SAM9G20 manages six Masters, which means that each master can
perform an access concurrently with others, according the slave it accesses is available.
Each Master has its own decoder that can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
• Burst Management
• One Address Decoder provided per Master
• Boot Mode Select
• Remap Command
• Allows Handling of Dynamic Exception Vectors
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
32-bit data interface
(Words)
or fixed default master
internal boot, one for external boot, one after remap
List of Bus Matrix Masters
ARM926
ARM926 Data
PDC
ISI Controller
Ethernet MAC
USB Host DMA
™
Instruction
6384B–ATARM–15-Dec-08