m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 200

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
Figure 16.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers
2
0
1
9
C
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
n
o r
3 .
1
u
, 1
3
p
UARTi Special Mode Register
b7
1
UARTi Transmit/Receive Control Register 1
NOTES:
b7
2
(
NOTES:
M
0
b6
1. The BBS bit is set to "0" by program. It is unchanged if set to "1".
2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal,
3. Refer to notes for the SU1HIM bit in the UiSMR2 register.
0
b6
1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register.
2. The UiLCH bit is enabled when the SMD2 to SMD0 bits are set to "001
3
6
UART2: timer A0 underflow signal, UART3: timer A3 underflow signal,
UART4: timer A4 underflow signal.
b5
2
I/O mode), "100
Set this bit to "0" when the SMD2 to SMD0 bits are set to "010
9-bit transfer data)
b5
C
b4
8 /
Page 177
b4
, 3
b3
b3
M
b2
b2
3
b1
2
b1
C
2
f o
"(UART mode, 7-bit transfer data), or "101
b0
8 /
b0
4
3
SCLKDIV
ABSCS
8
Symbol
ACSE
LSYN
) T
SCLKSTPB
/UiERE
IICM
ABC
BBS
SSS
8
UiRRM
UiLCH
Bit
UiIRS
Symbol
Symbol
U0SMR to U4SMR
RE
TE
RI
TI
Bit
Symbol
U0C1 to U4C1
Bus Conflict Detect
Sampling Clock Select Bit
Auto Clear Function Select
Bit for Transmit Enable Bit
Arbitration Lost Detect
Flag Control Bit
SCLL Sync Output
Enable Bit
I
Transmit Start
Condition Select Bit
Clock Divide
Synchronous Bit
Bus Busy Flag
2
Transmit
Enable Bit
Transmit Buffer
Empty Flag
Receive
Enable Bit
Receive
Complete Flag
UARTi Transmit
Interrupt Cause
Select Bit
UARTi
Continuous
Receive Mode
Enable Bit
Data Logic
Select Bit
Clock-Divided
Synchronous
Stop Bit /
Error Signal Output
Enable Bit
C Mode Select Bit
Bit Name
Bit Name
(i=0 to 4)
(1)
Address
036D
Address
0367
0: Transmit disable
1: Transmit enable
0: Data in the UiTB register
1: No data in the UiTB register
0: Receive disable
1: Receive enable
0: No data in the UiRB register
1: Data in the UiRB register
0: No data in the UiTB register (TI = 1)
1: Transmission is completed (TXEPT = 1)
0: Disables continuous receive mode to be entered
1: Enables continuous receive mode to be entered
0: Not inversed
1: Inverse
Clock-divided synchronous stop bit (special mode 3)
0: Stops synchronizing
1: Starts synchronizing
Error signal output enable bit (special mode 5)
0: Not output
1: Output
16,
16,
02ED
02E7
0: Except I
1: I
0: Update per bit
1: Update per byte
0: Stop condition detected
1: Start condition detected (Busy)
0: Disabled
1: Enabled
0: Rising edge of transfer clock
1: Timer Aj underflow
0: Not related to RxDi
1: Synchronized with RxDi
(Note 3)
0: No auto clear function
1: Auto clear at bus conflict
16,
16,
2
C mode
2
033D
" (UART mode, 8-bit transfer data).
0337
2
(i=0 to 4)
" (I
16,
16,
2
2
C mode
C mode) or "110
0327
032D
Function
Function
2
16,
" (clock synchronous serial
16,
02F7
02FD
(2)
16
16
2
After Reset
"(UART mode,
00
16
After Reset
0000 0010
RW
RW
RW
RW
RW
RW
RW
RW
RW
2
(1)
RW
RW
RW
RW
RW
RW
RW
RO
RO
16. Serial I/O