m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 295

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m30833fjgp

Manufacturer Part Number
m30833fjgp
Description
Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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R
R
M
e
E
3
. v
J
2
0
Figure 21.22 Time Measurement Function (2)
C
1
9
3 .
B
8 /
0
1
3
0
(1)
(3) Trigger signal when using the digital filter
3
(2)
J
G
4
a
o r
0 -
n
When selecting the rising edge as a time measurement trigger
When selecting both edges as a time measurement trigger
Trigger signal
after passing the
digital filter
3 .
f
INPCij pin input
(The DF1 to DF0 bits in the GiTMCR register =10
Base timer i
TMijR bit
GiTMj register
(The CTS1 to CTS0 bits=11
Base timer i
TMijR bit
f
INPCij pin input
GiTMj register
1
u
BTi
fi or f
(The CTS1 to CTS0 bits in the GiTMCR register (i=0,1, j=0 to 7)=01
BTi
INPCij pin
, 1
3
p
(1)
1
(1)
(
2
BTi
M
NOTES:
NOTES:
NOTES:
0
(1)
0
3
(2)
(2)
1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer increments
2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. The TM0jR register if the CAS bit is set to "1".
3. No interrupt is generated if the microcomputer receives a trigger signal when the TMijR bit is set to "1".
1. If the CAS bit in the GiBCR1 register is set to "1" (32-bit time measurement), the group 1 base timer
2. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. The TM0jR bit if the CAS bit is set to "1".
3. Input pulses applied to the INPCij pin require 1.5 f
1. f
6
2
the counter whenever the group 0 base timer overflows.
Howver, the value of the GiTMj register changes.
increments counter every time the group 0 base timer overflows.
BTi
C
8 /
Page 272
when the DF1 to DF0 bits are set to "10
"H"
, 3
"L"
"H"
"H"
"L"
"L"
"1"
"0"
"H"
"L"
"1"
"0"
M
3
n-2
n-2
2
C
f o
8 /
n-1
n-1
4
3
8
) T
8
n
n
Delayed by max. 1 clock
Signal, which does not match
three times, is stripped off
2
n+1
n+1
)
n
n+2
n+2
n
n+3
n+3
n+2
2
", and f
n+4
n+4
(Note 3)
BTi
n+5 n+6
n+5
1
clock cycles or more.
when to "11
n+5
(Note 3)
n+6
2
n+5
21. Intelligent I/O (Time Measurement Function)
or 11
n+6
n+7
n+7
2
".
n+8
n+8
2
)
The trigger signal is delayed
by the digital filter
n+9 n+10 n+11 n+12 n+13 n+14
n+9 n+10 n+11 n+12 n+13 n+14
Write "0" by program
if setting to "0"
n+8
n+8
2
)
Maximum 3.5 fi or f
clock cycles
n+12
Write "0" by program
if setting to "0"
BTi (1)

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