m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 239

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

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If the output level of the TxDi pin (i=0 to 4) differs from the input level of the RxDi pin, an interrupt request is
generated.
UART0 and UART3 are assigned software interrupt number 40. UART1 and UART4 are assigned number
41. When using the bus conflict detect function of UART0 or UART3, of UART1 or UART4, set the IFSR6
bit and the IFSR7 bit in the IFSR register accordingly.
When the ABSCS bit in the UiSMR register is set to "0" (rising edge of the transfer clock), it is determined,
on the rising edge of the transfer clock, if the output level of the TxD pin and the input level of the RxD pin
match. When the ABSCS bit is set to "1" (timer Aj underflow), it is determined when the timer Aj (timer A3
in UART0, timer A4 in UART1, timer A0 in UART2, timer A3 in UART3, the timer A4 in UART4) overflows.
Use the timer Aj in one-shot timer mode.
When the ACSE bit in the UiSMR register is set to "1" (automatic clear at bus conflict) and the IR bit in the
BCNiIC register to "1" (discrepancy detected), the TE bit is set to "0" (transmit disable).
When the SSS bit in the UiSMR register is set to "1" (synchronized with RxDi), the TxDi pin starts transmit-
ting data on the falling edge of the RxDi pin. Figure 16.28 shows bits associated with the bus conflict detect
function.
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16. Serial I/O (Special Function)