m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 226
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m30833fjgp
Manufacturer Part Number
m30833fjgp
Description
Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M30833FJGP.pdf
(527 pages)
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16.3.6 SDA Input
16.3.7 ACK, NACK
16.3.8 Transmit and Receive Reset
1
9
C
3 .
B
8 /
When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are
stored into bits 7 to 0 (D
When the IICM2 bit is set to "1", the first seven bits (D
in the UiRB register. Store the eighth bit (D
If the IICM bit in the UiSMR register is set to "1" and the CKPH bit is set to "1", the same data as that of
when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising
edge of the ninth bit of the transfer clock.
When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the
ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin outputs the value set in the
ACKD bit.
If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H")
on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the
SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock.
When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection.
When the STC bit in the UiSMR2 register is set to "1" (UARTi initialization enabled) and a start condition
is detected,
If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains
unchanged. Select the external clock as the transfer clock when using this function.
- the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift
- the receive shift register is reset and the first bit starts receiving when the next clock is input.
- the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes low ("L") on the falling edge
0
1
3
0
register. The first bit starts transmitting when the next clock is input. UARTi output value remains
unchanged between when clock is input and when data of the first bit is output. The value remains the
same value as when start condition was detected.
of the ninth bit of the transfer clock.
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Page 203
8 /
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7
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to D
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8 /
4
3
0
8
) in the UiRB register. The ninth bit (D
) T
8
0
) into bit 8 in the UiRB register.
7
to D
1
) of received data are stored into bits 6 to 0
8
) is ACK or NACK.
16. Serial I/O (Special Function)
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