m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 283

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
Figure 21.12 G2POCR0 to G2POCR7 and G3POCR0 to G3POCR7 Registers
2
0
1
9
C
3 .
B
8 /
0
1
3
0
Group i Waveform Generation Control Register j (i=2 to 3; j=0 to 7)
b7
3
NOTES:
J
G
4
a
0 -
n
o r
1. This setting is valid only for even channels. In SR waveform output mode, values written to the
2. This setting is valid only for channels 0 and 1 in the groups 2 and 3. To use ISTxD2 or IE
3. The inverse output function is the final step in the waveform generation process. If the INV bit is set to
4. The PRT bit is valid when the RTP bit is set to "1" (real-time port function used) and the PRP bit in the
5. When the RTP bit is set to "1", the value written to the MOD2 to MOD0 bits is ignored.
b6
3 .
1
u
corresponding odd channel (next channel after an even channel) are ignored. Even channels output
waveforms. Odd channels output no waveforms.
MOD2 to MOD0 bits in the G2POCR0 register to "111
to MOD0 bits in the G2POCR1 register to "111
in the channels 0 and 1.
To use ISTxD3, set the MOD2 to MOD0 bits in the G3POCR0 register to "111
output, set the MOD2 to MOD0 bits in the G3POCR1 register to"111
MOD0 bits to "111
"1" (output inversed), the output signal is "H" when the IVL bit is set to "0" (outputs "L" as an initial
value) and "L" when the IVL bit is set to "1" (outputs "H" as an initial value).
GiBCR1 register is set to "1" (parallel RTP output mode).
, 1
3
b5
p
1
2
(
M
b4
0
0
3
6
b3
2
C
Page 260
b2
8 /
, 3
b1
M
2
" except in the channels 0 and 1.
b0
3
2
C
f o
Symbol
MOD0
MOD1
MOD2
8 /
RLD
PRT
RTP
INV
IVL
Bit
4
Symbol
G2POCR0 to G2POCR3
G2POCR4 to G2POCR7
G3POCR0 to G3POCR3
G3POCR4 to G2POCR7
3
8
) T
8
Real-time Port Function
Select Bit
Inverse Output Function
Select Bit
Operation Mode
Select Bit
Parallel Real-time Port
Output Trigger
Select Bit
Output Initial Value
Select Bit
GiPOj Register Value
Reload Timing
Select Bit
Bit Name
(3)
(4)
(5)
2
". Do not set the MOD2 to MOD0 bits to "111
2
". To use ISCLK2 for an output, set the MOD2
Address
0150
0154
0190
0194
0: Not triggered by matching the base
1: Triggered by matching the base timer
0: Reloads the GiPOj register when
1: Reloads the GiPOj register when
b2
0: Outputs "L" as default value
1: Outputs "H" as default value
0: Not used
1: Used (RTP output mode or parallel
0: Output is not inversed
1: Output is inversed
0
0
0
0
1
1
1
1
16
16
16
16
b1
0
0
1
1
0
0
1
1
, 0151
, 0155
, 0191
, 0195
timer with the GiPO0 to GiPO7 registers
with the GiPO0 to GiPO7 registers
counter is written to
the base timer is reset
RTP output mode)
b0
0
1
0
1
0
1
0
1
: Single waveform output mode
: SR waveform output mode
: Inverse waveform output mode
: Do not set to this value
: Bit-modulation PWM mode
: Do not set to this value
: Do not set to this value
: Use a communication function
output
16
16
16
16
2
, 0152
, 0156
, 0192
, 0196
". Do not set the MOD2 to
(2)
Function
16
16
16
16
, 0153
, 0157
, 0193
, 0197
2
". To use ISCLK3 for an
16
16
16
16
OUT
After Reset
00
00
00
00
16
16
16
16
(1)
2
, set the
" except
RW
RW
RW
RW
RW
RW
RW
RW
RW
21. Intelligent I/O