m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 359

• Manufacturer Part Number: m30833fjgp
• Description: Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
• Manufacturer: Renesas Electronics Corporation.

R
R
M
e
E
3
. v
J
Figure 22.9 C0TSR Register
2
Figure 22.10 C0TEC Register
0
22.1.8 CAN0 Transmit Error Count Register (C0TEC Register)
1
C
22.1.7 CAN0 Time Stamp Register (C0TSR Register)
9
3 .
B
8 /
0
1
3
0
CAN0 Time Stamp Register
b15
3
CAN0 Transmit Error Count Register
The C0TSR register is a 16-bit counter. The TSPRE0 and TSPRE1 bits in the C0CTLR0 register
select the CAN bus bit clock divided by 1, 2, 3 or 4 as the count source for the C0TSR register.
When data transmission or reception is completed, the value of the C0TSR register is automatically
stored into the message slot.
The C0TSR register starts a counter increment when the RESET0 and RESET1 bits in the C0CTLR0
register are set to "0".
The C0TSR register is set to "0000
In loopback mode, when either data frame receive message slot or remote frame receive message
slot is available to store the message, the value of the C0TSR register is also stored into the mes-
sage slot when data reception is completed. The value of the C0TSR register is not stored when data
transmission is completed.
In an error active or an error passive state, the count value of a transmission error is stored into the
C0TEC register. The counter is decremented when the CAN module has transmitted data as ex-
pected or is incremented when an transmit error occurs.
In a bus-off state, an indeterminate value is stored into the C0TEC register. The C0TEC register is
set to "00
J
G
b7
NTOES:
4
a
NOTES:
0 -
o r
n
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
• at the next count timing after the C0TSR register is set to "FFFF
• when the RESET0 and RESET1 bits are set to "1" (CAN module reset) by program, or
• when the TSRESET bit is set to "1" (C0TSR register reset) by program.
3 .
1. Value is obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and
1
u
supplying a clock to the CAN module after reset.
, 1
3
p
supplying a clock to the CAN module after reset.
1
(
2
M
0
b8
16
0
3
6
2
b7
" when the CAN module is placed in an error active state again.
C
8 /
Page 336
, 3
M
3
b0
b0
2
C
f o
Counter Value of Transmit Errors
Value of Time Stamp
8 /
4
3
Symbol
C0TSR
8
Symbol
C0TEC
) T
8
16
":
Address
0209
Address
020A
16 -
16
0208
Function
16
Function
After reset
0000
After Reset
00
16
16
16
(1)
";
(1)
RW
RW
RO
RO
22. CAN Module