zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 102

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zl50019gag2

Manufacturer Part Number
zl50019gag2
Description
Enhanced 2 K Digital Switch With Stratum 4e Dpll
Manufacturer
Zarlink Semiconductor
Datasheet
16.384 Mbps
(16.384 MHz)
(16.384 MHz)
Input Frame Boundary
(4.096 MHz)
Input Frame Boundary
(8.192 MHz)
2.048 Mbps
4.096 Mbps
8.192 Mbps
STi0 - 31
STi0 - 31
STi0 - 31
STi0 - 31
Figure 35 - GCI-Bus Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps
CKi
CKi
CKi
FPi
CKi
FPi
FPi
FPi
Ch255
Figure 34 - ST-BUS Input Timing Diagram when Operated at 16 Mbps
Ch127
Bit1
Bit6
Ch31
Bit7
Ch255
Ch63
Bit0
Bit7
Ch127
Bit7
Bit7
Ch0
Ch0
Bit0
t
SIS16
t
SIS8
Bit0
Ch0
Bit6
Ch0
t
SIH16
Bit1
Ch0
Zarlink Semiconductor Inc.
t
SIH8
t
SIS4
ZL50019
Bit5
Ch0
t
SIH4
Bit2
Ch0
102
Ch0
Bit0
Ch0
Bit1
Ch0
Bit4
t
SIS2
Ch0
Bit3
t
SIH2
Ch0
Bit3
Ch0
Bit4
Ch0
Bit2
Ch0
Bit2
Ch0
Bit5
Bit1
Ch0
Bit6
Ch0
Ch0
Bit1
Bit3
Ch0
Bit0
Ch0
Bit7
Ch0
Data Sheet
V
V
CT
TT
V
V
V
V
CT
CT
CT
TT

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