zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 71

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

6 - 4
3 - 2
1 - 0
External Read Only Address: 004C
Bit
15
0
14
0
DPM1 - 0
RFR2 - 0
RES1 - 0
Table 37 - Reference Change Status Register (RCSR) Bits - Read Only (continued)
Name
13
0
Reference Frequency Indicator Bits
These bits represent the frequency of the selected reference indicated by the reference
bits (RES1 - 0) in this register.
Reference Select Indicator Bits: These bits indicate which one of the four reference
inputs (REF0 - 3 pins) is being selected by the device.
DPLL Timing Mode Status Bits:
These bits indicate the DPLL’s timing mode status.
12
0
H
11
0
RFR2
10
0
0
0
0
0
1
1
1
1
DPM1
RES1
0
0
1
1
0
0
1
1
9
0
Zarlink Semiconductor Inc.
RFR1
0
0
1
1
0
0
1
1
ZL50019
SLM
8
DPM0
RES0
0
1
0
1
0
1
0
1
71
RFR0
LST
0
1
0
1
0
1
0
1
7
Description
DPLL Timing Mode State
Input Reference in use
RFR2
Frequency of the Selected
6
Holdover
Freerun
Normal
REF 0
REF 1
REF 2
REF 3
MTIE
RFR1
16.384 MHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
Reference
19.44MHz
5
Reserved
8 kHz
RFR0
4
RES1
3
RES0
2
DPM1
Data Sheet
1
DPM0
0