zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 68

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

Note: The default value is ±56 ppm (’h099F/CFN = 56 ppm).
15 - 13
Reset Value: 2C00
Reset Value: 099F
Reset Value: 0000
External Read/Write Address: 0048
External Read/Write Address: 0049
External Read/Write Address: 004B
15 - 0
12 - 0
15 - 8
Bit
Bit
Bit
LDI
15
15
15
15
0
0
LDI
14
14
14
14
0
SRL12 - 0
0
LDI15 - 0
Unused
Unused
Name
Name
Name
H
H
H
LDI
13
13
13
13
(see Note)
0
0
SRL
Lock Detector Interval Bits
The binary value of these bits defines the time interval that the output phase detector
must be below the lock detect threshold to declare lock. Unsigned representation of the
LDI bits is defined in 4 ms intervals.
Reserved
In normal functional mode, these bits MUST be set to zero.
Slew Rate Limit Bits
The binary value of these bits defines the maximum rate of DPLL phase change (phase
slope), where the phase represents difference between the input reference and output
feedback clock. Defined in same units as CFN (unsigned).
Reserved
In normal functional mode, these bits MUST be set to zero.
LDI
12
12
12
Table 36 - Reference Change Control Register (RCCR) Bits
12
12
0
Table 34 - Lock Detector Interval Register (LDIR) Bits
H
H
H
Table 35 - Slew Rate Limit Register (SRLR) Bits
SRL
LDI
11
11
11
11
11
0
SRL
LDI
10
10
10
10
10
0
SRL
LDI
9
9
9
9
9
0
Zarlink Semiconductor Inc.
ZL50019
SRL
LDI
8
8
8
8
8
0
68
MTR
SRL
LDI
7
7
7
7
7
Description
Description
Description
SRL
PRS
LDI
6
6
6
6
6
1
PRS
SRL
LDI
5
5
5
5
5
0
PMS
SRL
LDI
4
4
4
4
4
2
PMS
SRL
LDI
3
3
3
3
3
1
PMS
SRL
LDI
2
2
2
2
2
0
Data Sheet
FDM
SRL
LDI
1
1
1
1
1
1
FDM
SRL
LDI
0
0
0
0
0
0