zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 47

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

17.3
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset. There
are two software reset bits in the Software Reset Register (SRR). SRSTDPLL (bit 0) is used to reset the DPLL while
SRSTSW (bit 1) resets the rest of the switch.
18.0
The ZL50019 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output
streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input
streams. Each transmitter can generate a BER sequence with a pattern of 2
Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1
frame time (125 µs). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and
TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled.
(This is the default state.)
Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be
transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER
receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies
has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how
many BER channels are to be monitored by the BER receiver.
For each input stream, there is a set of registers for the BER test. The registers are as follows:
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For normal BER operation, CMM (bit 0) must be 1 in the Connection Memory Low (CM_L). PCC1 - 0 (bits 2 - 1) in
the Connection Memory Low must be programmed to “10” to enable the per-stream based BER transmitters. For
each stream, the length (or total number of channels) of BER testing can be as long as one whole frame, but the
channels MUST be consecutive. Upon completion of programming the connection memory, the corresponding BER
receiver can be started by setting ST[n]SBER (bit 0) in the BRCR to high. There must be at least 2 frames (250 µs)
between completion of connection memory programming and starting the BER receiver before the BER receiver
can correctly identify BER errors. A 16 bit BER counter is used to count the number of bit errors.
BER Receiver Control Register (BRCR) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register
(BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver.
BER Receiver Start Register (BRSR) - ST[n]BRS7 - 0 (bit 7 - 0) defines the input channel from which the
BER sequence will start to be compared.
BER Receiver Length Register (BRLR) - ST[n]BL8 - 0 (bit 8 - 0) define how many channels the sequence
will last. Depending on the data rate being used, the BER test can last for a maximum of 32, 64, 128 or 256
channels at the data rates of 2.048, 4.096, 8.192 or 16.384 Mbps, respectively. The minimum length of the
BER test is a single channel. The user must take care to program the correct channel length for the BER test
so that the channel length does not exceed the total number of channels available in the stream.
BER Receiver Error Register (BRER) - This read-only register contains the number of counted errors. When
the error count reaches 0xFFFF, the BER counter will stop updating so that it will not overflow. ST[n]CBER
(bit 1) in the BER Receiver Control Register is used to reset the BRER register.
Software Reset
Pseudo Random Bit Generation and Error Detection
Zarlink Semiconductor Inc.
ZL50019
47
15
-1 pseudorandom code (ITU O.151).
Data Sheet