zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 63

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

Note: [n] denotes input stream from 16 - 31.
Reset Value: 0000
External Read/Write Address: 0040
15 - 0
15
15-6
0
Bit
4-2
Bit
External Read Address: 00014
Reset Value: 0000
5
1
0
BER
L31
15
14
0
ST4_LIM
Unused
Unused
DPLL_
Name
RFRE
BERL[n]
BER
L30
IRM
Name
14
H
13
0
H
Table 27 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only
BER
L29
13
12
0
Reserved
In normal functional mode, these bits MUST be set to zero.
Stratum 4E Limits Select Bit
When this bit is high, the stratum 4E limits are used for reference monitoring (i.e.,
+/-64.713 ppm and +/-82.487 ppm over 10 seconds).When this bit is low, more relaxed
Relaxed Stratum 4E limits are used for reference monitoring (i.e., +/-240 ppm and
+/-250 ppm over 10 seconds). This is used in applications where a low quality clock
(+/-100 ppm) is used as a reference.
Reserved
In normal functional mode, these bits MUST be set to zero.
Reference Frequency Register Enable
When this bit is low, the reference frequency value used in the DPLL comes from
appropriate reference frequency detector. When this bit is high, the reference frequency
value comes from Reference Frequency Register (RFR).
DPLL Internal Reset Mode
When this bit is low, the DPLL module is in the operational state. When this bit is high,
the DPLL module is in the power saving mode. Registers are not reset and are still
accessible in the power saving mode.
BER Receiver Lock[n]:
If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked.
If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
BER
L28
12
H
H
11
Table 28 - DPLL Control Register (DPLLCR) Bits
0
BER
L27
11
10
0
BER
L26
10
9
0
Zarlink Semiconductor Inc.
BER
L25
9
ZL50019
8
0
BER
L24
8
63
7
0
BER
L23
7
Description
Description
6
0
BER
L22
6
ST4_
LIM
BER
L21
5
5
BER
L20
4
0
4
BER
L19
3
3
0
BER
L18
2
2
0
BER
L17
1
RFRE
Data Sheet
1
BER
L16
0
DPLL
_IRM
0