zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 61

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

Note: [n] denotes input stream from 0 - 15.
15 - 2
15 - 0
External Read Address: 0010
Reset Value: 0000
Bit
Bit
External Read Address: 00011
Reset Value: 0000
1
0
BER
F15
15
OUTERR
15
BERF[n]
0
Unused
BER
INERR
F14
Name
Name
14
H
14
H
0
BER
F13
13
Table 24 - BER Error Flag Register 0 (BERFR0) Bits - Read Only
13
0
H
Reserved
In normal functional mode, these bits are zero.
Output Error (Read Only)
This bit is set high when the total number of output channels is programmed to be
more than the maximum capacity of 2048, in which case the output channels beyond
the maximum capacity should be disabled.
This bit will be cleared automatically after programming is corrected.
Input Error (Read Only)
This bit is set high when the total number of input channels is programmed to be more
than the maximum capacity of 2048, in which case the input channels beyond the
maximum capacity should be disabled.This bit will be cleared automatically after pro-
gramming is corrected.
BER Error Flag[n]:
If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not
zero.
If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Table 23 - Internal Flag Register (IFR) Bits - Read Only
BER
F12
12
H
12
0
BER
F11
11
11
0
BER
10
F10
0
10
9
0
Zarlink Semiconductor Inc.
BER
F9
9
ZL50019
8
0
BER
F8
8
61
7
0
BER
F7
7
6
0
Description
Description
BER
F6
5
0
6
BER
4
0
F5
5
3
0
BER
F4
4
2
0
BER
F3
3
OUT
ERR
1
BER
F2
2
ERR
IN
0
BER
F1
1
Data Sheet
BER
F0
0