zl50019gag2 Zarlink Semiconductor, zl50019gag2 Datasheet - Page 50

• Manufacturer Part Number: zl50019gag2
• Description: Enhanced 2 K Digital Switch With Stratum 4e Dpll
• Manufacturer: Zarlink Semiconductor

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21.2
The ZL50019 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a
four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP
Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDi and TDo during data register scanning.
21.3
As specified in the IEEE-1149.1 standard, the ZL50019 JTAG interface contains three test data registers:
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21.4
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE-1149.1 test interface.
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. The registers are
described in a subsequent section. The received input data is sampled at the rising edge of the TCK pulse.
This pin is internally pulled to high when it is not driven from an external source.
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or test data register are serially shifted out towards TDo. The data from TDo is
clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the
TDo driver is set to a high impedance state.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to high when it is not
driven from an external source.
The Boundary-Scan Register - The Boundary-Scan register consists of a series of boundary-scan cells
arranged to form a scan path around the boundary of the ZL50019 core logic.
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo.
The Device Identification Register - The JTAG device ID for the ZL50019 is 0C36314B
Instruction Register
Test Data Registers
BSDL
Version
Part Number
Manufacturer ID
LSB
<31:28>
<27:12>
<11:1>
<0>
Zarlink Semiconductor Inc.
ZL50019
50
0000
1100 0011 0110 0011
0001 0100 101
1
H
Data Sheet