at52sq1283j ATMEL Corporation, at52sq1283j Datasheet - Page 19

• Manufacturer Part Number: at52sq1283j
• Description: At52sq1283j 128-mbit Flash + 32-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

7. Command Definition Table
Notes:
3525B–STKD–3/05
Command Sequence
Read
Chip Erase
Plane Erase
Sector Erase
Word Program
Dual Word Program
Erase/Program Suspend
Erase/Program Resume
Product ID Entry
Sector Softlock
Sector Hardlock
Sector Unlock
Read Status Register
Clear Status Register
Program PR0 (Block B) or PR1
Lock Protection PR0 – Block B
Lock Protection PR1
Status of Protection PR0 (Block B)
Status of Protection PR1
Program Burst Configuration Register
Read Burst Configuration Register
CFI Query
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
2. PA is the plane address (A22 - A18). Any address within a plane can be used.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages
4. The first bus cycle address should be the same as the word address to be programmed.
5. This fast programming option enables the user to program two words in parallel only when V
6. During the second bus cycle, the manufacturer code is read from address PA+00000H, the device code is read from address
7. The plane address should be the same during the first and second bus cycle.
8. The status register bits are output on I/O7 - I/O0.
9. Any address within the user programmable protection register region. Please see
10. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
11. D
12. See
FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A22 through A8 are don’t care.
details).
Addr0 and Addr1, of the two words, D
manufacturing purposes only.
PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H and 00008AH - 000109H.
page
Addresses A16 - A22 can select any plane.
OUT
(6)(7)
“Burst Configuration Register” on page
20.
represents 16 bits of data. If all data bits are “0s”, the register is locked.
(5)
Cycles
Bus
1
2
2
2
2
3
1
1
1
2
2
2
2
1
2
2
2
2
2
2
2
1
IN0
and D
PA
(7)
21. Bits B15 - B0 of the burst configuration register determine A15 - A0.
000080
000089
Addr
Addr
Addr0
Addr
PA
SA
PA
PA
SA
SA
SA
PA
PA
+Addr
XX
XX
XX
XX
XX
XX
80
IN1
1st Bus Cycle
(2)
(2)
(2)
(2)
(7)
(3)
(3)
(3)
(3)
(4)
(9)
, must only differ in address A0. This command should be used during
(12)
40/10
Data
FF
E0
B0
D0
C0
C0
C0
21
22
20
90
60
60
60
70
50
90
90
60
90
98
PA
PAX005
(7)
000080
000089
Addr
Addr
Addr0
Addr
Addr
Addr
SA
SA
SA
SA
PA
+Addr
80
89
2nd Bus Cycle
(7)
(3)
(3)
(3)
(3)
(4)
(9)
(7)
(12)
“Protection Register Addressing Table” on
D
D
D
FFFD
Data
0000
D
OUT
OUT
D
OUT
D
D
D0
D0
D0
D0
01
2F
03
OUT
IN0
IN
IN
PP
(10)
(11)
(8)
AT52SQ1283J
= 9.5V. The addresses,
Addr1
Addr
3rd Bus Cycle
23
Data
D
-
26
IN1
for
19