at52sq1283j ATMEL Corporation, at52sq1283j Datasheet - Page 30

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at52sq1283j

Manufacturer Part Number
at52sq1283j
Description
At52sq1283j 128-mbit Flash + 32-mbit Psram Stack Memory
Manufacturer
ATMEL Corporation
Datasheet
22. AC Asynchronous Read Timing Characteristics
23. Page Read Cycle Waveform 1
Note:
24. Page Read Cycle Waveform 2
Note:
30
Symbol
t
t
t
t
t
t
t
t
t
t
t
ACC1
ACC2
CE
OE
AHAV
AVLP
AVHP
AAV
DF
RO
PAA
1. After the high-to-low transition on AVD, AVD may remain low as long as the page address is stable.
1. AVD may remain low as long as the page address is stable.
AT52SQ1283J
Parameter
Access, AVD To Data Valid
Access, Address to Data Valid
Access, CE to Data Valid
OE to Data Valid
Address Hold from AVD
AVD Low Pulse Width
AVD High Pulse Width
Address Valid to AVD
CE, OE High to Data Float
RESET to Output Delay
Page Address Access Time
I/O0-I/O15
A2 -A22
RESET
A0 -A1
I/O0-I/O15
AVD
OE
CE
A2 -A22
RESET
A0 -A1
(1)
AVD
OE
CE
(1)
t AVLP
t AVHP
t AAV
t AAV
t RO
t ACC2
t ACC2
t CE
t RO
t ACC2
t ACC2
t ACC1
t CE
t AHAV
t AHAV
(1)
(1)
t OE
t OE
DATA VALID
DATA VALID
t PAA
t PAA
Min
10
9
7
7
t DF
t DF
t DF
t DF
V IL
Max
150
70
70
70
20
25
30
3525B–STKD–3/05
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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