at52sq1283j ATMEL Corporation, at52sq1283j Datasheet - Page 4

• Manufacturer Part Number: at52sq1283j
• Description: At52sq1283j 128-mbit Flash + 32-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

6. 128-Mbit Flash Description
6.1
6.2
6.3
4
Command Sequences
Burst Configuration Command
Asynchronous Read
AT52SQ1283J
When the device is first powered on, it will be in the read mode. Command sequences are used
to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going
pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on
the AVD signal. If the AVD is not pulsed low, the address will be latched on the first rising edge of
the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever
occurs first. The addresses used in the command sequences are not affected by entering the
command sequences.
The Program Burst Configuration Register command is used to program the burst configuration
register shown on
control the read operation of the device. Bit B15 determines whether synchronous burst reads
are enabled or asynchronous reads are enabled. Since the page read operation is an asynchro-
nous operation, bit B15 must be set for asynchronous reads to enable the page read feature.
The rest of the bits in the burst configuration register are used only for the burst read mode. Bits
B13 - B11 of the burst configuration register determine the clock latency for the burst mode. The
latency can be set to two, three, four, five or six cycles. See the
Clock Frequency” on page
clock latency of four; the data is output from the device four clock cycles after the first valid clock
edge following the high-to-low AVD edge. The B10 bit of the configuration register determines
the polarity of the WAIT signal. The B9 bit of the burst configuration register determines the
number of clocks that data will be held valid (see
Data for 2 Clock Cycles Read Waveform is shown on
by the value of the B9 bit. The B8 bit of the burst configuration register determines when the
WAIT signal will be asserted. When synchronous burst reads are enabled, a linear burst
sequence is selected by setting bit B7. Bit B6 selects whether the burst starts and the data out-
put will be relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of the burst
configuration register determine whether a continuous or fixed-length burst will be used and also
determine whether a four-, eight- or sixteen-word length will be used in the fixed-length mode.
When a four-, eight- or sixteen-word burst length is selected, Bit B3 can be used to select
whether burst accesses wrap within the burst length boundary or whether they cross word
length boundaries to perform linear accesses (see
All other bits in the burst configuration register should be programmed as shown on
The default state (after power-up or reset) of the burst configuration register is also shown on
page
There are two types of asynchronous reads – AVD pulsed and standard asynchronous reads.
The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The out-
puts are put in the high-impedance state whenever CE or OE is high. This dual-line control gives
designers flexibility in preventing bus contention. The data at the address location defined by
A0 - A22 and captured by the AVD signal will be read when CE and OE are low. The address
location passes into the device when CE and AVD are low; the address is latched on the low-to-
21.
page
21. The burst configuration register determines several parameters that
21. The
“Burst Read Waveform”
“Output Configuration” on page
“Sequence and Burst Length” on page
page
32. The clock latency is not affected
as shown on
“Clock Latency versus Input
page 32
21). The Hold
3525B–STKD–3/05
illustrates a
page
22).
21.