at52sq1283j ATMEL Corporation, at52sq1283j Datasheet - Page 46

• Manufacturer Part Number: at52sq1283j
• Description: At52sq1283j 128-mbit Flash + 32-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

51. Page Write Cycle
(Address Controlled, ZZ = V
Notes:
46
1. A write occurs during the overlap (t
2. t
3. t
4. t
5. Do not access device with cycle timing shorter than t
AT52SQ1283J
asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write
ends at the earliest transition when PCS1 goes high and PWE goes high. The t
the end of write.
CW
AS
WR
is measured from the address valid to the beginning of write.
PUB, PLB
is measured from the PCS1 going low to end of write.
is measured from the end of write to the address change. t
Data In
Data Out
A4~ A20
A0~ A3
PCS1
WE
Data Undefined
High-Z
IH
t
AS
)
(3)
t
WHZ
t
WC
WP
) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with
Data Valid
t
DW
t
DH
t
PC
Data Valid
t
DW
t
DH
t
PC
RC
Data Valid
t
DW
(t
WC
t
DH
t
) for continuous periods > 20 µs.
MRC
t
PC
Data Valid
t
DW
WR
t
DH
applied in case a write ends as PCS1 or PWE going high.
t
PC
Data Valid
t
DW
t
DH
t
PC
t
Data Valid
DW
WP
t
DH
is measured from the beginning of write to
t
PC
Data Valid
t
DW
t
DH
t
PC
Data Valid
t
DW
t
t
DH
OW
High-Z
3525B–STKD–3/05