at52sq1283j ATMEL Corporation, at52sq1283j Datasheet - Page 45

• Manufacturer Part Number: at52sq1283j
• Description: At52sq1283j 128-mbit Flash + 32-mbit Psram Stack Memory
• Manufacturer: ATMEL Corporation

50. Write Cycle Waveforms
50.1
(PWE Controlled, ZZ = V
50.2
(PCS1 Controlled, ZZ = V
50.3
(PUB, PLB Controlled, ZZ = V
Notes:
3525B–STKD–3/05
Write Cycle (1)
Write Cycle (2)
Write Cycle (3)
1. A write occurs during the overlap (t
2. t
3. t
4. t
5. Do not access device with cycle timing shorter than t
asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write
ends at the earliest transition when PCS1 goes high and PWE goes high. The t
the end of write.
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the PCS1 going low to end of write.
is measured from the end of write to the address change. t
PUB, PLB
IH
Data Out
Address
IH
PUB, PLB
PUB, PLB
Data In
)
Data Out
Data Out
Address
Address
)
PCS1
Data In
PWE
Dat a In
PCS1
PCS1
PWE
PWE
IH
)
WP
Data Undefined
) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with
S
High-Z
High-Z
S
High-Z
S
RC
HZ
(t
WC
W
W
) for continuous periods > 20 µs.
(2)
W
(2)
C
C
C
W
W
W
(2)
W
W
P
W
WR
P
(1)
P
(1)
(1)
applied in case a write ends as PCS1 or PWE going high.
W
Data Valid
Data Valid
W
Data Valid
W
R
WP
(4)
W
R
is measured from the beginning of write to
(4)
R
(4)
High-Z
High-Z
High-Z
AT52SQ1283J
45