adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 10

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

ADSST-SHARC-Melody-Ultra
Target Board JTAG Emulator Connector
Analog Devices’ DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the SHARC Melody
Ultra processor to monitor and control the target board proces-
sor during emulation. Analog Devices’ DSP Tools product line
of JTAG emulators provides emulation at full processor speed,
enabling inspection and modification of memory, registers, and
processor stacks. The processor’s JTAG interface ensures that
the emulator will not affect target system loading or timing. For
complete information on Analog Devices’ DSP Tools product
line of JTAG emulator operation, see the appropriate Emulator
Hardware User's Guide. For detailed information on the inter-
facing of Analog Devices’ JTAG emulators with Analog Devices’
DSP products with JTAG emulation ports, please refer to the
Engineer-to-Engineer Note EE-68, Analog Devices JTAG Emula-
tion Technical Reference. Both of these documents can be found
on the Analog Devices website at:
http://www.analog.com/dsp/tech_docs.html.
DMA Controller
The SHARC Melody Ultra processor’s on-chip DMA controller
enables zero-overhead data transfers without processor inter-
vention. The DMA controller operates independently and
invisibly to the processor core, enabling DMA operations to
occur while the core is simultaneously executing its program
instructions. DMA transfers can occur between the SHARC
Melody Ultra processor’s internal memory and external mem-
ory, external peripherals, or a host processor. DMA transfers can
also occur between the SHARC Melody Ultra processor’s inter-
nal memory and its serial ports, link ports, or the SPI (serial
peripheral interface) compatible port. External bus packing and
unpacking of 16-, 32-, 48-, or 64-bit words in internal memory
is performed during DMA transfers from either 8-, 16-, or 32-
bit wide external memory. Fourteen channels of DMA are avail-
able on the SHARC Melody Ultra; two are shared between the
SPI interface and the link ports, eight via the serial ports, and
four via the processor’s external port (for either host processor,
other SHARC Melody Ultra’s memory or I/O transfers). Pro-
grams can be downloaded to the SHARC Melody Ultra using
DMA transfers. Asynchronous off-chip peripherals can control
two DMA channels using DMA request/grant lines ( DMAR 1–2,
DMAG 1–2). Other DMA features include interrupt generation
upon completion of DMA transfers, and DMA chaining for
automatic linked DMA transfers.
Multiprocessing
The SHARC Melody Ultra offers powerful features tailored to
multiprocessing DSP systems. The external port and link ports
provide integrated glueless multiprocessing support. The
external port supports a unified address space (see F
that enables direct interprocessor accesses of each SHARC
Melody Ultra processor’s internal memory-mapped (I/O
processor) registers. All other internal memory can be indirectly
accessed via DMA transfers initiated through the programming
igure 5
)
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of the IOP DMA parameter and control registers. Distributed
bus arbitration logic is included on-chip for simple, glueless
connection of systems containing up to six SHARC Melody
Ultra processors and a host processor. Master processor
changeover incurs only one cycle of overhead. Bus arbitration is
selectable as either fixed or rotating priority. Bus lock enables
indivisible read-modify-write sequences for semaphores. A
vector interrupt is provided for interprocessor commands. The
maximum throughput for interprocessor data transfers is
400 Mbytes/s over the external port. Two link ports provide a
second method of multiprocessing communications. Each link
port can support communications to another SHARC Melody
Ultra. The SHARC Melody Ultra running at 100 MHz has a
maximum throughput for interprocessor communications over
the links of 200 Mbytes/s. The link ports and cluster
multiprocessing can be used concurrently or independently.
Link Ports
The SHARC Melody Ultra features two 8-bit link ports that
provide additional I/O capabilities. With the capability of run-
ning at 100 MHz, each link port can support 100 Mbytes/s. Link
port I/O is especially useful for point-to-point interprocessor
communication in multiprocessing systems. The link ports can
operate independently and simultaneously, with a maximum
data throughput of 200 Mbytes/s. Link port data is packed into
48- or 32-bit words and can be directly read by the core proces-
sor, or DMA-transferred to on-chip memory. Each link port has
its own double-buffered input and output registers.
Clock/acknowledge handshaking controls link port transfers.
Transfers are programmable as either transmit or receive.
Serial Ports
The SHARC Melody Ultra features four synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices. Each serial port is
made up of two data lines, a clock, and frame sync. The data
lines can be programmed to either transmit or receive.
The serial ports operate at up to half the clock rate of the core,
providing each with a maximum data rate of 50 Mbps. The
serial data pins are programmable as either a transmitter or
receiver, providing greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via a dedicated DMA. Each of the serial ports
features a Time Division Multiplex (TDM) multichannel mode;
two serial ports are TDM transmitters and two serial ports are
TDM receivers (SPORT0 RX paired with SPORT2 TX, SPORT1
RX paired with SPORT3 TX). Each of the serial ports also
supports the I
commonly used by audio codecs, ADCs, and DACs), with two
data pins, enabling four I
devices) per serial port, up to a maximum of 16 I
The serial ports enable little-endian or big-endian transmission
formats and word lengths selectable from three bits to 32 bits.
For I
2
S mode, data-word lengths are selectable between eight
2
S protocol (an industry-standard interface
2
S channels (using two I
2
2
S stereo
S channels.