adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 21

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (AV
External (I/O) Supply Voltage (V
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Stresses greater than those listed above may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DDEXT
DD
DDINT
)
)
)
Rating
–0.3 V to +2.2 V
–0.3 V to +2.2 V
–0.3 V to +4.6 V
–0.5 V to V
–0.5 V to V
200 pF
–65°C to +150°C
DDEXT
DDEXT
+ 0.5 V
+ 0.5 V
Rev. 0 | Page 21 of 28
TIMING SPECIFICATIONS
The SHARC Melody Ultra processor’s internal clock switches at
higher frequencies than the system input clock (CLKIN). To
generate the internal clock, the processor uses an internal
phase-locked loop (PLL). This PLL based clocking minimizes
the skew between the system clock (CLKIN) signal and the
processor’s internal clock (the clock source for the external port
logic and I/O pads).
The SHARC Melody Ultra processor’s internal clock (a multiple
of CLKIN) provides the clock signal for timing internal mem-
ory, processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access mode).
During reset, program the ratio between the processor’s internal
clock frequency and external (CLKIN) clock frequency with the
CLK_CFG1–0 and CLKDBL pins. Even though the internal
clock is the clock source for the external port, it behaves as de-
scribed on the Clock Rate Ratio chart in the CLKDBL pin
description in
the serial and link ports, divide down the internal clock using
the programmable divider control of each port (DIVx for the
serial ports and LxCLKD for the link ports).
(4.2MHz–50MHz)
CRYSTAL OR
OSCILLATOR
CRYSTAL
QUARTZ
CLKIN
XTAL
Figure 13. Core Clock and System Relationship to CLKIN
Table 2
DOUBLER
CLKDBL
CLOCK
×1, ×2
ADSST-SHARC-Melody-Ultra
. To determine switching frequencies for
PLL
PLLICLK
(8.4MHz–50MHz)
CLK_CFG[1:0]
×2, ×3, ×4
RATIOS
CCLK
(33.3MHz
TO 100MHz)
MULTIPROCESSING
IO-PROCESSOR
×1/2, ×1 BY SW
SBSRAM
SRAM
HOST
×1, ×1/2, ×1/3,
LINK PORT:
×1/4 BY SW
EP:
CORE
SDRAM
EP:
CLKOUT
LCLK[1:0]
SDCLK[1:0]