adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 9

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

SHARC MELODY ULTRA MEMORY AND I/O
INTERFACE FEATURES
The SHARC Melody Ultra adds the following architectural fea-
tures to the ADSP-2116x family core:
Dual-Ported On-Chip Memory
The SHARC Melody Ultra contains 1 Mbit of on-chip SRAM,
organized as two blocks of 0.5 Mbits. Each block can be
configured for different combinations of code and data storage.
Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O processor.
The dual-ported memory in combination with three separate
on-chip buses enables two data transfers from the core and one
from the I/O processor, within a single cycle. On the SHARC
Melody Ultra, the memory can be configured as a maximum of
32 Kwords of 32-bit data, 64 Kwords of 16-bit data, 21 Kwords
of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 1 Mbit. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively
doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit
floating-point formats is done in a single instruction. While
each memory block can store combinations of code and data,
access is most efficient when one block stores data using the
DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers. Using the DM bus and
PM bus, with one dedicated to each memory block, assures
single-cycle execution with two data transfers. In this case, the
instruction must be available in the cache.
Off-Chip Memory and Peripherals Interface
The SHARC Melody Ultra’s external port provides the proces-
sor’s interface to off-chip memory and peripherals. The
62.7 Mword off-chip address space (254 Mword if all SDRAM)
is included in the SHARC Melody Ultra processor’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data—are multiplexed at the external port to create an external
system bus with a single 24-bit address bus and a single 32-bit
data bus. Every access to external memory is based on an ad-
dress that fetches a 32-bit word. When fetching an instruction
from external memory, two 32-bit data locations are being ac-
cessed for packed instructions. Unused link port lines can also
be used as additional data lines DATA[0]–DATA[15], enabling
single-cycle execution of instructions from external memory at
up to 100 MHz.
cesses to external memory.
Figure 6
shows the alignment of various ac-
Rev. 0 | Page 9 of 28
The external port supports asynchronous, synchronous, and
synchronous burst access. Synchronous burst SRAM can be
interfaced gluelessly. The SHARC Melody Ultra can also inter-
face gluelessly to SDRAM. Addressing of an external memory
device is facilitated by on-chip decoding of high-order address
lines to generate memory bank select signals. The SHARC Mel-
ody Ultra provides programmable memory wait states and
external memory acknowledge controls to enable interfacing to
memory and peripherals with variable access, hold, and disable
time requirements.
SDRAM Interface
The SDRAM interface enables the SHARC Melody Ultra to
transfer data to and from synchronous DRAM (SDRAM) at the
core clock frequency or one-half the core clock frequency. The
synchronous approach, coupled with the core clock frequency,
supports data transfer at a high throughput—up to
400 Mbytes/s for 32-bit transfers and 600 Mbytes/s for 48-bit
transfers. The SDRAM interface provides a glueless interface
with standard SDRAMs (16 Mbit, 64 Mbit, 128 Mbit, and
256 Mbit) and includes options to support additional buffers
between the SHARC Melody Ultra and SDRAM. The SDRAM
interface is extremely flexible and provides capability for con-
necting SDRAMs to any one of the SHARC Melody Ultra
processor’s four external memory banks, with up to all four
banks mapped to SDRAM. Systems with several SDRAM de-
vices connected in parallel may require buffering to meet
overall system timing requirements. The SHARC Melody Ultra
supports pipelining of the address and control signals to enable
such buffering between itself and multiple SDRAM devices.
47
FLOAT OR FIXED, D31–D0, 32-BIT PACKED
32-BIT PACKED INSTRUCTION
40 39
16-BIT PACKED INSTRUCTION EXECUTION
Figure 6. External Data Alignment Options
8-BIT PACKED INSTRUCTION EXECUTION
48-BIT INSTRUCTION FETCH
(NO PACKING)
16-BIT PACKED DMA DATA
ADSST-SHARC-Melody-Ultra
DATA 47
32 31
8-BIT PACKED DMA DATA
–
16
24 23
PROM BOOT
16 15
EXTRA DATA LINES DATA[15
ARE ONLY ACCESSIBLE IF
LINK PORTS ARE DISABLED.
ENABLE THESE ADDITIONAL
DATA LINES BY SELECTING
IPACK[1:0] = 01 IN SYSCON
L1DATA[7:0]
DATA 15 – 8
DATA 15
8 7
L0DATA[7:0]
DATA7 – 0
–
0
–
0]
0