adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 23

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. t
and with ∆V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
∆V to be the difference between the SHARC Melody Ultra
processor’s output voltage and the input threshold for the device
requiring the hold time. A typical ∆V will be 0.4 V. C
total bus capacitance (per data line) and I
three-state current (per data line). The hold time will be t
plus the minimum disable time.
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 16). Figure 18 shows how output
delays and holds vary with load capacitance. (Note that this
graph or derating does not apply to output disable delays; see
REFERENCE
(MEASURED)
(MEASURED)
SIGNAL
OUTPUT
PIN
TO
V
V
OH
OL
t
DIS
OUTPUT
Figure 16. Equivalent Device Loading for AC Measurements
INPUT
Figure 17. Voltage Reference Levels for AC Measurements
OR
OUTPUT STOPS DRIVING
DECAY
1.5V
Figure 15. Output Enable/Disable
(Except Output Enable/Disable)
using the equation given previously. Choose
DECAY
t
MEASURED
V
V
OH
OL
(Includes All Fixtures)
t
DECAY
VOLTAGE TO BE APPROXIMATELY 1.5V.
(MEASURED) + ∆V
(MEASURED) – ∆V
is calculated with test loads C
TEST CONDITIONS CAUSE THIS
HIGH-IMPEDANCE STATE.
30pF
t
L
ENA
is the total leakage or
OUTPUT STARTS DRIVING
50Ω
2.0V
1.0V
(MEASURED)
(MEASURED)
L
1.5V
is the
L
V
V
and I
OH
OL
DECAY
1.5V
Rev. 0 | Page 23 of 28
L
,
the Output Disable Time section.) The graphs of Figure 18,
Figure 19, and Figure 20 may not be linear outside the ranges
shown for Typical Output Delay vs. Load Capacitance and Typi-
cal Output Rise/Fall Time (20%–80%, V = Min) vs. Load
Capacitance.
NOMINAL
Figure 19. Typical Output Rise/Fall Time (20%–80%, V
Figure 20. Typical Output Rise/Fall Time (20%–80%, V
Figure 18. Typical Output Delay or Hold vs. Load Capacitance
25
20
15
10
–5
16
14
12
10
16
14
12
10
5
8
6
4
2
8
6
4
2
0
0
0
0
0
20
20
ADSST-SHARC-Melody-Ultra
30
40
40
(at Max Case Temperature)
Y = 0.0835X – 2.42
60
Y = 0.0743X + 1.5613
Y = 0.0773X + 1.4399
60
60
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
80
RISE TIME
80
RISE TIME
90
100
100
Y = 0.0414X + 2.0128
Y = 0.0417X + 1.8674
120
120
120
FALL TIME
FALL TIME
140
140
150
160
160
DDEXT
DDEXT
180
180
180
= Max)
= Min)
200
210
200