adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 11

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

bits and 32 bits. Serial ports offer selectable synchronization and
transmit modes as well as optional µ-law or A-law companding.
Serial port clocks and frame syncs can be internally or exter-
nally generated.
Serial Peripheral (Compatible) Interface
Serial Peripheral Interface (SPI) is an industry-standard syn-
chronous serial link, enabling the SHARC Melody Ultra SPI
compatible port to communicate with other SPI compatible
devices. SPI is a 4-wire interface consisting of two data pins, one
device select pin, and one clock pin. It is a full-duplex synchro-
nous serial interface, supporting both master and slave modes.
The SPI port can operate in a multimaster environment by in-
terfacing with up to four other SPI compatible devices, acting as
either a master or slave device. The SHARC Melody Ultra SPI
compatible peripheral implementation also features program-
mable baud rate and clock phase/polarities. The SHARC
Melody Ultra SPI compatible port uses open-drain drivers to
support a multimaster configuration and to avoid data conten-
tion.
Host Processor Interface
The SHARC Melody Ultra host interface enables easy connec-
tion to standard 8-bit, 16-bit, or 32-bit microprocessor buses
with little additional hardware required. The host interface is
accessed through the SHARC Melody Ultra’s external port. Four
channels of DMA are available for the host interface; code and
data transfers are accomplished with low software overhead.
The host processor requests the SHARC Melody Ultra’s external
bus with the host bus request ( HBR ), host bus grant ( HBG ), and
ready (REDY) signals. The host can directly read and write the
internal IOP registers of the SHARC Melody Ultra, and can
access the DMA channel setup and message registers. DMA
setup via a host would enable it to access any internal memory
address via DMA transfers. Vector interrupt support provides
efficient execution of host commands.
General-Purpose I/O Ports
The SHARC Melody Ultra also contains 12 programmable, gen-
eral-purpose I/O pins that can function as either inputs or
outputs. As outputs, these pins can signal peripheral devices; as
inputs, these pins can provide the test for conditional branch-
ing.
Program Booting
The internal memory of the SHARC Melody Ultra can be
booted at system power-up from either an 8-bit EPROM, a host
processor, the SPI interface, or through one of the link ports.
Selection of the boot source is controlled by the Boot Memory
Select ( BMS ), EBOOT (EPROM Boot), and Link/Host Boot
(LBOOT) pins. 8-, 16-, or 32-bit host processors can also be
used for booting.
Rev. 0 | Page 11 of 28
Phased-Locked Loop and Crystal Double Enable
The SHARC Melody Ultra uses an on-chip phase-locked loop
(PLL) to generate the internal clock for the core. The
CLK_CFG[1:0] pins are used to select ratios of 2:1, 3:1, and 4:1.
In addition to the PLL ratios, the CLKDBL pin can be used for
more clock ratio options. The (1×/2× CLKIN) rate set by the
CLKDBL pin determines the rate of the PLL input clock and the
rate at which the synchronous external port operates. With the
combination of CLK_CFG[1:0] and CLKDBL , ratios of 2:1, 3:1,
4:1, 6:1, and 8:1 between the core and CLKIN are supported. See
Figure 13.
CLOCK
RESET
Figure 7. Shared Memory Multiprocessing System
3
2
1
ADSST-SHARC-Melody-Ultra
CLKIN
ID2
ID2
CLKIN
ID2
RESET
CLKIN
RESET
RESET
ADSP-21161 #4
ADSP-21161 #3
ADSP-21161 #2
ADSP-21161 #1
–
–
–
0
0
0
SDCLK[1
DATA47
DATA47
DATA47
ADDR23
CONTROL
ADDR23
CONTROL
ADDR23
SDCKE
SDA10
MS3
BR6
SDWE
REDY
SBTS
BMS
HBG
DQM
ACK
HBR
RAS
CAS
BR1
–
–
–
WR
RD
CS
–
16
–
16
–
16
–
–
–
0]
0
0
0
0
2
ADDR
DATA
CS
ADDR
DATA
OE
WE
ACK
CS
ADDR
DATA
RAS
CAS
DQM
WE
CLK
CKE
A10
CS
ADDR
DATA
PERIPHERALS
(OPTIONAL)
PROCESSOR
INTERFACE
(OPTIONAL)
MEMORY
(OPTIONAL)
(OPTIONAL)
GLOBAL
EPROM
AND
SDRAM
HOST
BOOT