adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 5

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

The block diagram of the SHARC Melody Ultra (see
illustrates the following architectural features:
We will use F
communicates with the host microcontroller using SPI. The
SHARC Melody Ultra has an on-chip memory buffer that is
used for storing commands/parameters sent by the host to the
SHARC Melody Ultra and status information from the SHARC
Melody Ultra. There is a defined protocol for passing com-
mands and obtaining status information. Once the SHARC
Melody Ultra receives a command from the host micro, it will
process the command and inform the host micro about the
status. These commands initiate actions such as encoding and
decoding. Encoding and decoding will result in data processing
and the processed data may be delivered over the serial port.
For example, while encoding, the MP3 data is accepted through
the serial port from peripherals like an ADC or S/PDIF receiver.
The MP3 data is then encoded and stored in an on-chip com-
pressed data buffer. The SHARC Melody Ultra will prepare the
compressed frames in IEC 958 format so that they can be sent
out using the serial port or S/PDIF transmitter. Using the serial
port, compressed frames can be downloaded to the SHARC
Melody Ultra where they can be decoded, and the resulting
MP3 data can be sent on the serial port transmitter. While
commands and data are transferred between the host microcon-
troller and the SHARC Melody Ultra over the SPI, reliable
communication needs the help of interrupts and a few general-
purpose input/output lines.
SOFTWARE ARCHITECTURE
The audio processors from Analog Devices enable designers to
make value additions to product features working off the high-
end base functionality. The SHARC Melody Ultra software has
the following parts:
• Computation units (ALU, multiplier, and shifter) with a
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• Timers with event capture modes
• On-chip, dual-ported SRAM
• External port for interfacing to off-chip memory and pe-
• Host port and SDRAM interface
• DMA controller
• Enhanced serial ports
• JTAG test access port
• Executive kernel
• Algorithm as library module
shared data register file
ripherals
igure 2
as our reference. The SHARC Melody Ultra
Figure 1
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)
The executive kernel has the following functions:
The executive kernel is executed as soon as booting takes place.
The hardware resources are initialized in the beginning. The
command buffer and general-purpose programmable flag pins
are initialized. Various data buffers and memory variables are
initialized. Interrupts are programmed and enabled. Then, defi-
nite signatures are written “Command buffer” to inform the
host that the SHARC Melody Ultra is ready to receive the com-
mands. Once commands are issued by the host microcontroller,
they are executed and appropriate actions take place. Decoding
is handled by issuing appropriate commands from the host
microcontroller.
The kernel communicates with the library module for a particu-
lar algorithm in a defined way. The details are found in the
specific implementation documents. As the kernel is modular, it
is easy to customize to different hardware platforms. Most of
the time, users need to change the initialization code to suit the
particular codec chosen.
The SHARC Melody Ultra includes a 100 MHz core, dual-
ported on-chip SRAM, an integrated I/O processor with multi-
processing support, and multiple internal buses to eliminate I/O
bottlenecks. The SHARC Melody Ultra offers a Single-
Instruction-Multiple-Data (SIMD) architecture, using two
computational units. Fabricated in a state of the art, high speed,
low power CMOS process, the SHARC Melody Ultra has a 10 ns
instruction cycle time.
With its SIMD computational hardware running at 100 MHz,
the SHARC Melody Ultra can perform 600 million math opera-
tions per second.
the SHARC Melody Ultra.
INPUT STREAM
• Power-up hardware initialization
• Serial port management
• Automatic stream detect
• Automatic code load
• Command processing
• Interrupt handling
• Data buffer management
• Calling library module
• Status report
ADSST-SHARC-Melody-Ultra
Table 1
EXECUTIVE KERNEL
Figure 3. Software
shows performance benchmarks for
DECODING
LIBRARY
OUTPUT STREAM