adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 4

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

ADSST-SHARC-Melody-Ultra
GENERAL DESCRIPTION
The SHARC Melody Ultra family of powerful 32-bit audio
processors from Analog Devices enables flexible designs and
delivers a host of features across high-end and high fidelity
audio systems to the AV receiver and DVD markets. It includes
multichannel audio decoders, encoders, and postprocessors for
digital audio designs using DSPs in home theater systems and
automotive audio receivers.
With 32-bit audio quality, the SHARC Melody Ultra audio
processor autodetects and decodes audio formats in real time,
enabling end users to enjoy a theater-quality audio experience
in their homes and automobiles.
The designs can be customized to meet the exact requirements
of the application. This audio DSP system enables designers to
make value additions to product features working off the high-
end base functionality with which they are provided.
Evaluation boards, sample applications and all necessary soft-
ware support (e.g., drivers) are available. The evaluation board
enables OEMs to offer comprehensive and single-chip imple-
mentations of advanced features for end-user products. SHARC
Melody Ultra audio processors enable OEMs to produce high
quality, low cost designs featuring decoder algorithms and post-
processors for DTS-ES Extended Surround (including both
DTS Discrete 6.1 and DTS Matrix 6.1), DTS Neo:6, Dolby Digi-
tal, Dolby Pro Logic II, Dolby Headphone, Dolby Virtual
Speaker Technology, THX Ultra2, HDCD, MPEG1 Audio Layer
3 (also known as MP 3), MPEG2 multichannel, AAC, WaveSur-
round, SRS Labs’ Circle Surround II, and stereo. It additionally
includes audio encoders for DDCE.
The cost of development is reduced, enabling common solu-
tions across product lines. Field and remotely upgradeable
products with programmable DSPs and an optimized library of
routines, along with the best development tools in the industry,
reduce the time to market.
SHARC Melody Ultra is the comprehensive answer to the needs
of the high-end, high quality digital audio market. It delivers a
realistic high fidelity audio experience along with the maximum
number of features in the product, across price points in the
high-end home theater and DVD markets.
HARDWARE ARCHITECTURE
Hardware architecture includes the interface between the DSP
and the host microcontroller, command processing, data
transfer in serial and parallel form, data buffer management,
algorithm combinations, MIPS, and memory requirements that
are provided.
The multichannel algorithms are implemented on a SHARC
Melody Ultra AVR evaluation board. The board is standalone
and accepts a compressed digital bit stream as serial input from
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LD/DVD/CD players or stream generators, decodes the bit
stream, and generates a PCM stream in real time in 2-channel
or multichannel mode. It has a microcontroller to handle com-
mands and option selections from a small keypad and an LCD
display for status display.
To understand the SHARC Melody Ultra family hardware archi-
tecture, one should examine its four major blocks:
The hardware architecture of the SHARC Melody Ultra is com-
plex. It has four independent buses for dual data, one for
instructions, and one for I/O fetch. Since the four buses are in-
dependent, multiple transactions take place within a single
clock cycle. It has two external ports, DMA channels, and eight
serial ports. It is a 0.35 ns technology IC operating at 3.3 V.
The SHARC Melody Ultra processor can be interfaced to exter-
nal peripherals with relative ease. The communication between
the SHARC Melody Ultra processor and a host microcontroller
utilizes the SPI bus. The host microcontroller can be the master
and the SHARC Melody Ultra processor can act as a slave. The
peripherals can be controlled by the host microcontroller using
the SPI bus. The communication is based on commands and
parameters. Status information regarding the SHARC Melody
Ultra decoding is periodically updated and made available to
the host microcontroller.
• The Core Processor
• Dual-Ported SRAM
• External Port
• Input/Output Processor
TRANSMITTER
RECEIVER
S/PDIF
S/PDIF
ADC
DAC
BOOT ROM
128k × 32,
SDRAM
1M × 8
Figure 2. Simplified Block Diagram
SERIAL PORT
GPIO
IRQ
CHANNEL
CODEC
MULTI-
HOST MICRO
KERNEL
COMMAND