adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 17

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

Mnemonic
LxDAT7–0
[DATA15–0]
MISO
MOSI
MS3–0
NC
PA
RAS
RD
REDY
RESET
RPBA
RSTOUT
SBTS
Type
I/O
[I/O/T]
I/O (O/D)
I/O (O/D)
I/O/T
I/O/T
I/O/T
I/O/T
O (O/D)
I/A
I/S
O
I/S
Function
Link Port Data (Link Ports 0–1).
For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when used as a data
pin, or a 20 kΩ internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.
For silicon revisions 0.3, 1.0, and 1.1, each LxDAT pin has a 50 kΩ internal pull-down resistor that is enabled or
disabled by the LxPDRDE bit of the LCTL register.
Note that L1DATA[7:0] are multiplexed with the DATA[15:8] pins; L0DATA[7:0] are multiplexed with the
DATA[7:0] pins. If link ports are disabled and are not be used, these pins can be used as additional data lines
for executing instructions at up to the full clock rate from external memory. See DATA47–16 for more
information.
SPI Master In Slave Out. If the SHARC Melody Ultra is configured as a master, the MISO pin becomes a data
receive (input) pin. If the SHARC Melody Ultra is configured as a slave, the MISO pin becomes a data transmit
(output) pin. In a SHARC Melody Ultra SPI interconnection, the data is shifted out from the MISO output pin of
the slave and shifted into the MISO input pin of the master. MISO has an internal pull-up resistor. MISO can be
configured as O/D by setting the OPD bit in the SPICTL register.
Note that only one slave is enabled to transmit data at any given time.
SPI Master Out Slave In. If the SHARC Melody Ultra is configured as a master, the MOSI pin becomes a data
transmit (output) pin. If the SHARC Melody Ultra is configured as a slave, the MOSI pin becomes a data
receive (input) pin. In a SHARC Melody Ultra SPI interconnection, the data is shifted out from the MOSI output
pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal pull-up resistor.
Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of
external memory. Memory bank sizes are fixed to 16 Mwords for non-SDRAM and 64 Mwords for SDRAM. The
MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs
transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the
other address lines; however, they de-assert after the first CLKIN cycle in which ACK is sampled asserted. In a
multiprocessor systems, the MSx signals are tracked by slave SHARCs. The internal addresses 24 and 26 are
zeros and 26 and 27 are decoded into MS3–0.
Do Not Connect. Reserved pins that must be left open and unconnected (5 pins).
Priority Access. Asserting its PA pin enables a SHARC Melody Ultra bus slave to interrupt background DMA
transfers and gain access to the external bus. PA is connected to all SHARC Melody Ultra processors in the
system. If access priority is not required in a system, the PA pin should be left unconnected. PA has a 20 kΩ
internal pull-up resistor that is enabled for DSPs with ID2–0 = 00x.
SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, this pin
defines the operation for the SDRAM to perform.
Memory Read Strobe. RD is asserted whenever the SHARC Melody Ultra reads a word from external memory
or from the IOP registers of other SHARC Melody Ultra processors. External devices, including other SHARC
Melody Ultra processors, must assert RD for reading a word of the SHARC Melody Ultra IOP register memory.
In a multiprocessing system, RD is driven by the bus master. RD has a 20 kΩ internal pull-up resistor that is
enabled for DSPs with ID2–0 = 00x.
Host Bus Acknowledge. The SHARC Melody Ultra deasserts REDY (low) to add wait states to a host access of
its IOP registers when CS and HBR inputs are asserted.
Processor Reset. Resets the SHARC Melody Ultra to a known state and begins execution at the program
memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at
power-up.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection that must be set to the same value on every SHARC Melody Ultra. If the value of RPBA is changed
during system operation, it must be changed in the same CLKIN cycle on every SHARC Melody Ultra.
Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in reset. It is deasserted
4096 cycles after RESET is deasserted indicating that the PLL is stable and locked. (RSTOUT exists only for
silicon revision 1.2.)
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address,
data, selects, and strobes in a high impedance state for the following cycle. If the SHARC Melody Ultra
attempts to access external memory while SBTS is asserted, the processor will halt and the memory access
will not be completed until SBTS is deasserted. SBTS should only be used to recover from host
processor/SHARC Melody Ultra deadlock.
Rev. 0 | Page 17 of 28
ADSST-SHARC-Melody-Ultra