adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 14

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

ADSST-SHARC-Melody-Ultra
The following symbols appear in the Type column of
Table 2. Pin Function Description
Mnemonic
ACK
ADDR23–0
AGND
AV
BMS
BMSTR
BR6–1
BRST
CAS
DD
A
G
I
O
P
S
(A/D)
(O/D)
T
Asynchronous,
Ground,
Input,
Power Supply,
Synchronous,
Active Drive,
Open Drain,
Three-State (when SBTS is asserted or
when the SHARC Melody Ultra is a bus
slave).
Output,
Type
I/O/S
I/O/T
G
P
I/O/T
O
I/O/S
I/O/T
I/O/T
Function
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The SHARC Melody Ultra deasserts ACK as an output to add wait states to a
synchronous access of its IOP registers. ACK has a 20 kΩ internal pull-up resistor that is enabled during reset
or on DSPs with ID2–0 = 00x.
External Bus Address. The SHARC Melody Ultra outputs addresses for external memory and peripherals on
these pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the IOP registers
of other SHARC Melody Ultra processors, while all other internal memory resources can be accessed indirectly
via DMA control (that is, accessing IOP DMA parameter registers). The SHARC Melody Ultra inputs addresses
when a host processor or multiprocessing bus master is reading or writing its IOP registers. A keeper latch on
the DSP’s ADDR23–0 pins maintains the input at the level to which it was last driven. This latch is only
enabled on the SHARC Melody Ultra with ID2–0 = 00x.
Analog Power Supply Return.
Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock generator). This pin
has the same specifications as V
section.
Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins; see
on page 18. This input is a system configuration selection that should be hardwired. For Host and EPROM
boot, DMA Channel 10 (EPB0) is used. For Link boot and SPI boot, DMA Channel 8 is used. Three-state only in
EPROM boot mode (when BMS is an output).
Bus Master Output. In a multiprocessor system, indicates whether the SHARC Melody Ultra is current bus
master of the shared external bus. The SHARC Melody Ultra drives BMSTR high only while it is the bus master.
In a single-processor system (ID = 000), the processor drives this pin high.
Multiprocessing Bus Requests. Used by multiprocessing SHARC Melody Ultra processors to arbitrate for bus
mastership. A SHARC Melody Ultra only drives its own BRx line (corresponding to the value of its ID2–0
inputs) and monitors all others. In a multiprocessor system with less than six SHARC Melody Ultra processors,
the unused BRx pins should be pulled high; the processor’s own BRx line must not be pulled high or low
because it is an output.
Sequential Burst Access. BRST is asserted by SHARC Melody Ultra to indicate that data associated with
consecutive addresses is being read or written. A slave device samples the initial address and increments an
internal address counter after each transfer. The incremented address is not pipelined on the bus. A master
SHARC Melody Ultra in a multiprocessor environment can read slave external port buffers (EPBx) using the
burst protocol. BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after
that, except for the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch
on the DSP’s BRST pin maintains the input at the level to which it was last driven. This latch is only enabled on
the SHARC Melody Ultra with ID2–0 = 00x.
SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,
defines the operation for the SDRAM to perform.
Table 2
Rev. 0 | Page 14 of 28
:
DDINT
, except that added filtering circuitry is required. See the Power Supplies
Unlike previous SHARC processors, the SHARC Melody Ultra
contains internal series resistance equivalent to 50 Ω on all in-
put/output drivers except the CLKIN and XTAL pins. Therefore,
for traces longer than six inches, external series resistors on
control, data, clock, or frame sync pins are not required to
dampen reflections from transmission line effects for point-to-
point connections. However, for more complex networks such
as star configurations, series termination is still recommended.
Table 3