adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 15

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

Mnemonic
CLK_CFG1–0
CLKDBL
CLKIN
CLKOUT
CS
DATA47–16
Type
I
I
I
O/T
I/A
I/O/T
Function
Core/CLKIN Ratio Control. SHARC Melody Ultra core clock (instruction cycle) rate is equal to n × PLLICLK
where n is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs. These pins can also be used in
combination with the CLKDBL pin to generate additional core clock rates of 6 × CLKIN and 8 × CLKIN (see the
Clock Rate Ratios table in the CLKDBL description).
Crystal Double Mode Enable. This pin is used to enable the 2× clock double circuitry, where CLKOUT can be
configured as either 1× or 2× the rate of CLKIN. This CLKIN double circuit is primarily intended to be used for
an external crystal in conjunction with the internal clock generator and the XTAL pin. The internal clock
generator, when used in conjunction with the XTAL pin and an external crystal, is designed to support up to a
maximum of 25 MHz external crystal frequency. CLKDBL can be used in XTAL mode to generate a 50 MHz
input into the PLL. The 2× clock mode is enabled (during RESET low) by tying CLKDBL to GND, otherwise it is
connected to V
100 MHz core clock rates and a 50 MHz CLKOUT operation when CLK_CFG1= 0, CLK_CFG1= 0, and CLKDBL
clock rate ratio options (up to 100 MHz) for either CLKIN (external clock oscillator) or XTAL (crystal input) are
as follows:
Clock Rate Ratios
An 8:1 ratio enables the use of a 12.5 MHz crystal to generate a 100 MHz core (instruction clock) rate and a
25 MHz CLKOUT (external port) clock rate. See Figure 13.
Note that when using an external crystal, the maximum crystal frequency cannot exceed 25 MHz. For all
other external clock sources, the maximum CLKIN frequency is 50 MHz.
Local Clock In. Used in conjunction with XTAL. CLKIN is the SHARC Melody Ultra clock input. It configures the
SHARC Melody Ultra to use either its internal clock generator or an external clock source. Connecting the
necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external
clock to CLKIN while leaving XTAL unconnected configures the SHARC Melody Ultra to use the external clock
source such as an external clock oscillator.The SHARC Melody Ultra external port cycles at the frequency of
CLKIN. The instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up via the
CLK_CFG1–0 pins. CLKIN may not be halted, changed, or operated below the specified frequency.
Local Clock Out. CLKOUT is 1× or 2× and is driven at either 1× or 2× the frequency of CLKIN frequency by the
current bus master. The frequency is determined by the CLKDBL pin. This output is three-stated when the
SHARC Melody Ultra is not the bus master or when the host controls the bus (HBG asserted). A keeper latch
on the DSP’s CLKOUT pin maintains the output at the level to which it was last driven. This latch is only
enabled on the SHARC Melody Ultra with ID2–0 = 00x.
If CLKDBL enabled, CLKOUT = 2 × CLKIN
If CLKDBL disabled, CLKOUT = 1 × CLKIN
Note that CLKOUT is controlled only by the CLKDBL pin and operates at either 1 × CLKIN or 2 × CLKIN.
Do not use CLKOUT in multiprocessing systems; use CLKIN instead.
Chip Select. Asserted by host processor to select the SHARC Melody Ultra.
External Bus Data. The SHARC Melody Ultra inputs and outputs data and instructions on these pins. Pull-up
resistors on unused data pins are not necessary. A keeper latch on the DSP’s DATA47–16 pins maintains the
input at the level to which it was last driven. This latch is only enabled on the SHARC Melody Ultra with ID2–0
= 00x.
Note that DATA[15:8] pins (multiplexed with L1DATA[7:0]) can also be used to extend the data bus if the link
ports are disabled and will not be used. In addition, DATA[7:0] pins (multiplexed with L0DATA[7:0]) can also
be used to extend the data bus if the link ports are not used. This enables execution of 48-bit instructions
from external SBSRAM (system clock speed-external port), SRAM (system clock speed-external port) and
SDRAM (core clock or one-half the core clock speed). The IPACKx instruction packing mode bits in SYSCON
should be set correctly (IPACK1–0 = 0x1) to enable this full instruction width/no-packing mode of operation.
= 0. This pin can also be used to generate different clock rate ratios for external clock oscillators. The possible
CLKDBL
1
1
0
0
0
0
CLK_CFG1
0
0
1
0
0
1
DDEXT
for 1× clock mode. For example, this enables the use of a 25 MHz crystal to enable
CLK_CFG0
0
1
0
0
1
0
Rev. 0 | Page 15 of 28
Core:CLKIN
2:1
3:1
4:1
4:1
6:1
8:1
CLKIN:CLKOUT
1×
1×
1×
2×
2×
2×
ADSST-SHARC-Melody-Ultra