k4b2g0446e Samsung Semiconductor, Inc., k4b2g0446e Datasheet
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... K4B2G0446E K4B2G0846E DDP 2Gb E-die DDR3 SDRAM Specification 78 FBGA with Lead-Free & Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4B2G0446E K4B2G0846E Revision History Revision Month Year 1.0 March 2009 - First release DDP 2Gb DDR3 SDRAM History Page Rev. 1.0 March 2009 ...
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... K4B2G0446E K4B2G0846E Table Contents 1.0 Ordering Information ................................................................................................................... 5 2.0 Key Features ................................................................................................................................ 5 3.0 Package pinout/Mechanical Dimension & Addressing ............................................................ 6 3.1 x4 DDP Package Pinout (Top view) : 78ball FBGA Package 3.2 x8 DDP Package Pinout (Top view) : 78ball FBGA Package 3.3 FBGA Package Dimension (x4) 3.4 FBGA Package Dimension (x8) 4.0 Input/Output Functional Description ....................................................................................... 10 5.0 DDR3 SDRAM Addressing ........................................................................................................ 11 6 ...
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... K4B2G0446E K4B2G0846E 9.9 ODT Timing Definitions 9.9.1 Test Load for ODT Timings 9.9.2 ODT Timing Definition 10.0 IDD Specification Parameters and Test Conditions ............................................................. 28 10.1 IDD Measurement Conditions 10.2 IDD Specifications definition 11.0 DDP 2Gb DDR3 SDRAM E-die IDD Spec Table ..................................................................... 37 12.0 Input/Output Capacitance ....................................................................................................... 38 13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 .............................. 39 ...
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... The 2Gb DDR3 E-die device is available in 78ball FBGAs(x4/x8). Note : 1. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. 85°C, 3.9us at CASE Page DDP 2Gb DDR3 SDRAM DDR3-1333 (9-9-9) Package K4B2G0446E-MCH9 78 FBGA K4B2G0846E-MCH9 78 FBGA DDR3-1333 Unit 9-9-9 1.5 ns ...
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... K4B2G0446E K4B2G0846E 3.0 Package pinout/Mechanical Dimension & Addressing 3.1 x4 DDP Package Pinout (Top view) : 78ball FBGA Package DDQ V D SSQ V E REFDQ F ODT1 G ODT0 H CS1 Ball Locations (x4) Populated ball Ball not populated ...
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... K4B2G0446E K4B2G0846E 3.2 x8 DDP Package Pinout (Top view) : 78ball FBGA Package DDQ V D SSQ V E REFDQ F ODT1 G ODT0 H CS1 Ball Locations (x8) Populated ball Ball not populated Top view (See the balls through the package) ...
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... K4B2G0446E K4B2G0846E 3.3 FBGA Package Dimension (x4) (Datum A) (Datum ∅0.45 Solder ball (Post Reflow ∅0.50 ± 0.05) 0.2 #A1 9.00 ± 0. 6.40 #A1 INDEX MARK 0.80 1.60 3. BOTTOM VIEW 9.00 ± 0.10 TOP VIEW Page DDP 2Gb DDR3 SDRAM ...
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... K4B2G0446E K4B2G0846E 3.4 FBGA Package Dimension (x8) (Datum A) (Datum ∅0.45 Solder ball (Post Reflow ∅0.50 ± 0.05) 0.2 #A1 9.00 ± 0. 6.40 #A1 INDEX MARK 0.80 1.60 3. BOTTOM VIEW 9.00 ± 0.10 TOP VIEW Page DDP 2Gb DDR3 SDRAM ...
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... K4B2G0446E K4B2G0846E 4.0 Input/Output Functional Description [ Table 3 ] Input/Output function description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of CK, CK Input the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers ...
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... K4B2G0446E K4B2G0846E 5.0 DDR3 SDRAM Addressing 1Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly *1 Page size 2Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly *1 Page size 4Gb Configuration # of Bank Bank Address ...
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... K4B2G0446E K4B2G0846E 6.0 Absolute Maximum Ratings 6.1 Absolute Maximum DC Ratings [ Table 4 ] Absolute Maximum DC Ratings Symbol Parameter V Voltage on V pin relative to Vss Voltage on V pin relative to Vss DDQ DDQ V V Voltage on any pin relative to Vss IN, OUT T Storage Temperature STG Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... K4B2G0446E K4B2G0846E 8.0 AC & DC Input Measurement Levels 8.1 AC and DC Logic input levels for single-ended singnals [ Table 7 ] Single Ended AC and DC input levels for Command and Address Symbol Parameter V (DC) DC input logic high IH.CA V (DC) DC input logic low IL.CA V (AC) AC input logic high IH.CA V (AC) AC input logic low IL ...
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... K4B2G0446E K4B2G0846E 8.2 V Tolerances REF The dc-tolerance limits and ac-noise limits for the reference voltages function of time. (V stands for V REF REF V (DC) is the linear average of V (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in table 7. Fur- ...
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... K4B2G0446E K4B2G0846E 8.3 AC and DC Logic Input Levels for Ditterential Signals 8.3.1 Differential signal definition V .DIFF.AC.MIN .DIFF.MAX IL V .DIFF.AC.MAX IL Figure 2 : Definition of differential ac-swing and "time above ac level" tDVAC 8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) [ Table 9 ] Defferential AC and DC Input Levels ...
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... K4B2G0446E K4B2G0846E 8.3.3 Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach V SEH half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach V preceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’ ...
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... K4B2G0446E K4B2G0846E 8.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V ...
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... K4B2G0446E K4B2G0846E 9.0 AC and DC Output Measurement Levels 9.1 Single Ended AC and DC Output Levels [ Table 14 ] Single Ended AC and DC output levels Symbol Parameter V (DC) DC output high measurement level (for IV curve linearity (DC) DC output mid measurement level (for IV curve linearity (DC) DC output low measurement level (for IV curve linearity) ...
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... K4B2G0446E K4B2G0846E 9.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V V (AC) for differential signals as shown inTable 18 and figure 7. OHdiff [ Table 18 ] Differential Output slew rate definition Description ...
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... K4B2G0446E K4B2G0846E 9.6 Overshoot/Undershoot Specification 9.6.1 Address and Control Overshoot and Undershoot specifications [ Table overshoot/undershoot specification for Address and Control pins (A0-A12, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 9) Maximum peak amplitude allowed for undershoot area (See Figure 9) ...
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... K4B2G0446E K4B2G0846E 9.7 34 ohm Output Driver DC Electrical Characteristics A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ as follows: RON = RZQ/7 (Nominal 34ohms +/- 10% with nominal RZQ=240ohm) 34 RON = RZQ/6 (Nominal 40ohms +/- 10% with nominal RZQ=240ohm) 40 The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows ...
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... K4B2G0446E K4B2G0846E 9.7.1 Output Drive Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to table 23 and 24. ∆ T(@calibration); ∆ DDQ DDQ *dR dT and dR dV are not subject to production test but are verified by design and characterization ...
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... K4B2G0446E K4B2G0846E 9.8.1 ODT DC electrical characteristics Table 26 provides and overview of the ODT DC electrical characteristics. They values for RTT RTT RTT RTT RTT 40pu80, 30pd60, 30pu60, 20pd40, [ Table 25 ] ODT DC Electrical characteristics, assuming RZQ=240 ohm +/- 1% entire operationg temperature range ; after proper ZQ calibration. MR1 (A9,A6,A2) RTT ...
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... K4B2G0446E K4B2G0846E Note : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that V 3 ...
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... K4B2G0446E K4B2G0846E 9.9 ODT Timing Definitions 9.9.1 Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in Figgure 13. CK,CK 9.9.2 ODT Timing Definition Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 28 and subsequent figures. Measurement reference settings are provided in Table 29 ...
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... K4B2G0446E K4B2G0846E Begin point : Rising edge defined by the end point of ODTLon CK CK DQ, DM DQS , DQS TDQS , TDQS V SSQ Figure 14. Definition of tAON Begin point : Rising edge with ODT being first registered high CK CK DQ, DM DQS , DQS TDQS , TDQS V SSQ Figure 15. Definition of tAONPD ...
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... K4B2G0446E K4B2G0846E Begin point : Rising edge with ODT being first registered low RTT_Nom DQ, DM DQS , DQS V SW2 TDQS , TDQS V SW1 Figure 17. Definition of tAOFPD Begin point : Rising edge defined by the end point of ODTLcnw RTT_Nom End point DQ, DM Extrapolated point ...
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... K4B2G0446E K4B2G0846E 10.0 IDD Specification Parameters and Test Conditions 10.1 IDD Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and IDDQ measurements. - IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all V IDD currents ...
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... K4B2G0446E K4B2G0846E [ Table 31 ] Basic IDD and IDDQ Measurement Conditions Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8 IDD0 Inputs: partially toggling according to Table 32 ; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ...
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... K4B2G0446E K4B2G0846E [ Table 31 ] Basic IDD and IDDQ Measurement Conditions Symbol Description Self-Refresh Current: Extended Temperature Range (optional) TCASE 95°C; Auto Self-Refresh (ASR): Disabled IDD6ET a) LOW; CL: see Table AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: Extended Temperature Self-Refresh operation ...
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... K4B2G0446E K4B2G0846E RESET CK/CK CKE CS RAS, CAS ODT [Note: DIMM level Output test load condition may be different from above ] Figure 19 : Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements Application specific memory channel environment Channel IO Power ...
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... K4B2G0446E K4B2G0846E [ Table 32 ] IDD0 Measurement - Loop Pattern 0 0 ACT 1 3 ... repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS PRE ... repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC + 0 ACT 1*nRC + 1*nRC + ... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary ...
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... K4B2G0446E K4B2G0846E [ Table 33 ] IDD1 Measurement - Loop Pattern 0 0 ACT 1 3 ... repeat pattern 1...4 until nRCD- 1, truncate if necessary nRCD ... repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS PRE ... repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 1*nRC + 1*nRC + ...
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... K4B2G0446E K4B2G0846E [ Table 35 ] IDD2NT and IDDQ2NT Measurement - Loop Pattern 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2: 8-11 repeat Sub-Loop 0, but ODT = 0 and BA[2: 12-15 repeat Sub-Loop 0, but ODT = 0 and BA[2: 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2: 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2: ...
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... K4B2G0446E K4B2G0846E [ Table 37 ] IDD4W Measurement - Loop Pattern 2,3 D 6,7 D,D 1 8-15 repeat Sub-Loop 0, but BA[2: 16-23 repeat Sub-Loop 0, but BA[2: 24-31 repeat Sub-Loop 0, but BA[2: 32-39 repeat Sub-Loop 0, but BA[2: 40-47 repeat Sub-Loop 0, but BA[2: 48-55 repeat Sub-Loop 0, but BA[2: 56-63 repeat Sub-Loop 0, but BA[2: Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. ...
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... K4B2G0446E K4B2G0846E [ Table 39 ] IDD7 Measurement - Loop Pattern 0 ACT 1 RDA 0 2 ... repeat above D Command until nRRD - 1 nRRD ACT nRRD + 1 RDA 1 nRRD + 2 ... repeat above D Command until 2*nRRD nRRD repeat Sub-Loop 0, but BA[2: nRRD repeat Sub-Loop 1, but BA[2: nRRD Assert and repeat above D Command until nFAW - 1, if necessary ...
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... IDD0 85 IDD1 100 IDD2P0(slow exit) 20 IDD2P1(fast exit) 50 IDD2N 60 IDD2NT 60 IDD2Q 50 IDD3P(fast exit) 50 IDD3N 70 IDD4R 125 IDD4W 115 IDD5B 180 IDD6 20 IDD7 200 512Mx4 (K4B2G0446E) DDR3-1066 DDR3-1333 7-7-7 9-9-9 90 100 105 115 130 150 135 160 180 ...
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... K4B2G0446E K4B2G0846E 12.0 Input/Output Capacitance [ Table 41 ] Input/Output Capacitance Parameter Input/output capacitance (DQ, DM, DQS, DQS, TDQS, TDQS) Input capacitance (CK and CK) Input capacitance delta (CK and CK) Input capacitance (All other input-only pins) Input capacitance delta (DQS and DQS) Input capacitance delta CDI_CTRL (All control input-only pins) ...
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... K4B2G0446E K4B2G0846E 13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 13.1 Clock specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the DDR3 SDRAM device. 13.1.1 Definition for tCK (avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge ...
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... K4B2G0446E K4B2G0846E 13.2 Refresh Parameters by Device Density [ Table 42 ] Refresh parameters by device density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval Note : 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material ...
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... K4B2G0446E K4B2G0846E [ Table 45 ] DDR3-1333 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = CWL = 6 CWL = 7 CWL = CWL = 6 CWL = 7 CWL = 5 ...
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... K4B2G0446E K4B2G0846E [ Table 46 ] DDR3-1600 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = CWL = 6 CWL = 7, 8 CWL = 5 CWL = CWL = 7 ...
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... K4B2G0446E K4B2G0846E 13.3.1 Speed Bin Table Notes Absolute Specification ( OPER DDQ DD Note : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be ful- filled: Requirements from CL setting as well as requirements from CWL setting. ...
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... K4B2G0446E K4B2G0846E 14.0 Timing Parameters by Speed Grade [ Table 47 ] Timing Parameters by Speed Bin Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period ...
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... K4B2G0446E K4B2G0846E [ Tabel 47 ] Timing Parameters by Speed Bin (Cont.) Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time ...
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... K4B2G0446E K4B2G0846E [ Table 47 ] Timing Parameters by Speed Bin (Cont.) Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid com- mand;Exit Percharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to com- ...
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... K4B2G0446E K4B2G0846E 14.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm tCK(avg) + tERR(4per),min ...
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... K4B2G0446E K4B2G0846E 14.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent programmed in mode register 5. Value must be rounded-up to next higher integer value 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. For definition of RTT turn-on time tAON see " ...
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... K4B2G0446E K4B2G0846E 14.3 Address / Command Setup, Hold and Derating: For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see Table 48) to the ∆tIS and ∆tIH derating value (see Table 49) respectively. ...
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... K4B2G0446E K4B2G0846E [ Table 50 ] Derating values DDR3-1333/1600 tIS/tIH-ac/dc based - Alternate AC150 Threshold Alternate AC150 Threshold -> V 4.0 V/ns 3.0 V/ns ∆tIS ∆tIH ∆tIS CMD/ 0 ADD Slew 0.8 0 -10 0 rate 0.7 0 -16 0 V/ns 0.6 -1 -26 -1 0.5 -10 -40 -10 0.4 -25 -60 -25 [ Table 51 ] Required time t above V VAC Slew Rate[V/ns] > ...
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... K4B2G0446E K4B2G0846E Note :Clock and Strobe are drawn on a different time scale DQS DQS V DDQ V (AC) min IH V (DC) min IH V (DC) REF V (DC) max IL V (AC) max Setup Slew Rate Falling Signal Figure 21 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock) ...
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... K4B2G0446E K4B2G0846E Note :Clock and Strobe are drawn on a different time scale DQS DQS V DDQ V (AC) min IH V (DC) min IH V (DC) REF V (DC) max IL V (AC) max Hold Slew Rate Rising Signal Figure 22 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock) ...
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... K4B2G0446E K4B2G0846E Note :Clock and Strobe are drawn on a different time scale DQS DQS V DDQ V (AC) min IH V (DC) min IH V (DC) REF V (DC) max IL V (AC) max IL nominal V SS Setup Slew Rate Falling Signal Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS ...
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... K4B2G0446E K4B2G0846E Note :Clock and Strobe are drawn on a different time scale DQS DQS V DDQ V (AC) min IH V (DC) min IH V (DC) REF V (DC) max IL V (AC) max Hold Slew Rate tangent line [ V Rising Signal Figure 24 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH ...
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... K4B2G0446E K4B2G0846E 14.4 Data Setup, Hold and Slew Rate Derating: or all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see Table 52) to the ∆ tDS and ∆tDH (see Table 53) derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS. ...
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... K4B2G0446E K4B2G0846E Note :Clock and Strobe are drawn on a different time scale DQS DQS V DDQ V (AC) min IH V (DC) min IH V (DC) REF V (DC) max IL V (AC) max Setup Slew Rate Falling Signal Figure 25 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock) ...
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... K4B2G0446E K4B2G0846E Note :Clock and Strobe are drawn on a different time scale DQS DQS V DDQ V (AC) min IH V (DC) min IH V (DC) REF V (DC) max IL V (AC) max Hold Slew Rate Rising Signal Figure 26 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock) ...
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... K4B2G0446E K4B2G0846E Note :Clock and Strobe are drawn on a different time scale DQS DQS V DDQ V (AC) min IH V (DC) min IH V (DC) REF V (DC) max IL V (AC) max IL nominal V SS Setup Slew Rate Falling Signal Figure 27 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS ...
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... K4B2G0446E K4B2G0846E Note :Clock and Strobe are drawn on a different time scale DQS DQS V DDQ V (AC) min IH V (DC) min IH V (DC) REF V (DC) max IL V (AC) max Hold Slew Rate tangent line [ V Rising Signal Figure 28 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH ...