k4b2g0446e Samsung Semiconductor, Inc., k4b2g0446e Datasheet - Page 55

• Manufacturer Part Number: k4b2g0446e
• Description: Ddp 2gb E-die Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4B2G0446E
K4B2G0846E
14.4 Data Setup, Hold and Slew Rate Derating:
or all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see
Table 52) to the ∆ tDS and ∆tDH (see Table 53) derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
(see Figure 25). If the actual signal is always earlier than the nominal slew rate line between shaded ’V
derating value. If the actual signal is later than the nominal slew rate line anywhere
between shaded ’V
Figure 27).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
(see Figure 26). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to V
derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V
line to the actual signal from the dc level to V
For a valid transition the input signal has to remain above/below V
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V
transition) a valid input signal is still required to complete the transition and reach V
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization
[ Table 52 ] Data Setup and Hold Base-Value
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
[ Table 53 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-ac/dc based
Note : a. Cell contents shaded in red are defined as ’not supported’.
[ Table 54 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition
DDR3
DDR3
1333/
1066
1600
800/
-
-
tDS(AC150)
Slew
Slew
V/ns
V/ns
rate
rate
tDH(base)
tDS(base)
DQ
DQ
Slew Rate[V/ns]
[ps]
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
>2.0
<0.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
REF
∆tDS
(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
88
59
75
50
0
0
-
-
-
-
-
-
-
-
-
-
-
-
4.0 V/ns
∆tDH
50
34
50
34
0
0
-
-
-
-
-
-
-
-
-
-
-
-
DDR3-800
75+50
150
∆tDS
75
88
59
75
50
-2
0
0
0
-
-
-
-
-
-
-
-
-
-
3.0 V/ns
REF
∆tDH
(DC) level is used for derating value (see Figure 28).
50
34
50
34
-4
-4
0
0
-
-
-
-
-
-
-
-
-
-
min
75
57
50
38
34
29
22
13
0
0
t
VAC
∆tDS, ∆tDH Derating [ps] AC/DC based
∆tDS
88
59
75
50
-2
-6
0
0
0
0
[ps] DDR3-800/1066
-
-
-
-
-
-
-
-
2.0 V/ns
DDR3-1066
25+50
100
∆tDH
25
-10
-10
50
34
50
34
-4
-4
0
0
-
-
-
-
-
-
-
-
IH/IL
Page 55 of 59
(AC) for some time tVAC (see Table 54).
DQS,DQS Differential Slew Rate
∆tDS
67
58
-3
8
6
2
8
8
8
8
-
-
-
-
-
-
-
-
1.8 V/ns
max
∆tDH
-
-
-
-
-
-
-
-
-
-
42
42
-2
-8
-2
-8
8
4
8
4
-
-
-
-
-
-
-
-
IH/IL
DDR3-1333
(AC).
30
65
∆tDS
-
16
14
10
16
16
16
16
15
-1
5
-
-
-
-
-
-
-
-
1.6 V/ns
∆tDH
a
-10
-10
16
12
16
12
6
0
6
0
-
-
-
-
-
-
-
-
DDP 2Gb DDR3 SDRAM
REF
∆tDS
-11
IL
22
18
13
24
24
24
23
14
REF
7
IH
-
-
-
-
-
-
-
-
REF
1.4V/ns
min
(DC) to ac region’, use nominal slew rate for
(DC)max and the first crossing of V
175
170
167
163
162
161
159
155
155
150
DDR3-1600
(DC)min and the first crossing of V
REF
t
(DC) and the first crossing of V
REF
(DC) and the first crossing of V
VAC
10
45
∆tDH
(DC) region’, the slew rate of a tangent
-
-16
-16
(DC) region’, use nominal slew rate for
20
14
20
14
IH/IL
[ps] DDR3-1333/1600
-2
-2
8
8
-
-
-
-
-
-
-
-
(AC) at the time of the rising clock
Rev. 1.0 March 2009
∆tDS
-30
26
21
15
32
32
31
22
-2
7
-
-
-
-
-
-
-
-
1.2V/ns
∆tDH
-26
-26
24
18
24
18
-6
-6
8
8
-
-
-
-
-
-
-
-
reference
V
V
V
IH/L
max
IH/L
IH/L
∆tDS
-
-
-
-
-
-
-
-
-
-
-22
29
23
40
39
30
15
(DC)
(AC)
(AC)
6
-
-
-
-
-
-
-
-
-
-
1.0V/ns
IH
IL
(AC)min.
(AC)max
REF
REF
∆tDH
-10
-10
(DC).
34
24
10
34
24
10
(DC)
-
-
-
-
-
-
-
-
-
-