k4b2g0446e Samsung Semiconductor, Inc., k4b2g0446e Datasheet - Page 16

• Manufacturer Part Number: k4b2g0446e
• Description: Ddp 2gb E-die Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4B2G0446E
K4B2G0846E
8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach V
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach V
preceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V
nals, then these ac-levels apply also for the single-ended signals CK and CK .
Note that while ADD/CMD and DQ signal requirements are with respect to V
with respect to V
ended components of differential signals the requirement to reach V
mode charateristics of these signals.
[ Table 11 ] Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Notes:
1. For CK, CK use V
2. V
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (V
Specification"
signal group, then the reduced level applies also here
IH
Symbol
(AC)/V
V
V
IH
SEH
SEL
(DC) max, V
IL
(AC) for DQs is based on V
DD
/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
IH
/V
Single-ended high-level for strobes
Single-ended high-level for CK, CK
IL
Single-ended low-level for strobes
Single-ended low-level for CK, CK
(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
IL
V
(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use V
DD
V
/2 or V
V
DD
SS
V
V
SEL
or V
SEH
or V
Parameter
DDQ
max
DDQ
SSQ
min
/2
REFDQ
SEH
Figure 3 : Single-ended requirement for differential signals.
min / V
; V
SEH
IH
(AC)/V
SEL
min / V
max (approximately equal to the ac-levels ( V
IL
SEL
(AC) for ADD/CMD is based on V
max (approximately the ac-levels ( V
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SEL
V
SEH
(V
(V
max, V
DD
DD
Note3
Note3
REF
/2)+0.175
/2)+0.175
Min
SEH
, the single-ended components of differential signals have a requirement
min has no bearing on timing, but adds a restriction on the common
DDR3-800/1066/1333/1600
REFCA
IH
; if a reduced ac-high or ac-low level is used for a
DDP 2Gb DDR3 SDRAM
IH
(AC) / V
IH
V
(AC) / V
150(AC)/V
SEL
IH
(V
(V
/V
IL
DD
DD
IL
(AC) ) for DQ signals) in every half-cycle
(AC) of DQs.
IL
Note3
Note3
Max
/2)-0.175
/2)-0.175
(AC) ) for ADD/CMD signals) in every
CK or DQS
IL
150(AC) is used for ADD/CMD sig-
Rev. 1.0 March 2009
time
Unit
V
V
V
V
Notes
1, 2
1, 2
1, 2
1, 2