k4b2g0446e Samsung Semiconductor, Inc., k4b2g0446e Datasheet - Page 28

• Manufacturer Part Number: k4b2g0446e
• Description: Ddp 2gb E-die Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4B2G0446E
K4B2G0846E
10.0 IDD Specification Parameters and Test Conditions
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and
- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and
- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all V
Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO
For IDD and IDDQ measurements, the following definitions apply :
- "0" and "LOW" is defined as V
- "1" and "HIGH" is defined as V
- "FLOATING" is defined as inputs are V
- Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 30.
- Basic IDD and IDDQ Measurement Conditions are described in Table 31.
- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 33 through Table 39.
- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}
Timing parameters are listed in the following table:
[ Table 30 ] Timing used for IDD and IDDQ Measured-Loop Patterns.
IDDQ measurements.
tCKmin(IDD)
CL(IDD)
tRCDmin(IDD)
tRCmin(IDD)
tRASmin(IDD)
tRPmin(IDD)
tFAW(IDD)
tRRD(IDD)
tRFC(IDD) - 512Mb
tRFC(IDD) - 1Gb
tRFC(IDD) - 2Gb
tRFC(IDD) - 4Gb
tRFC(IDD) - 8Gb
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
IDD7) are measured as time-averaged currents with all V
IDD currents.
together. Any IDD current is not included in IDDQ currents.
Parameter
power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since V
are using one merged-power layer in Module PCB.
x4/x8
x4/x8
Bin
x16
x16
5-5-5
DDR3-800
20
5
5
5
IN
IN
120
140
2.5
15
16
20
36
44
64
4
4
<= V
>= V
6-6-6
21
6
6
6
IL
IH
AC(max).
REF
AC(min).
6-6-6
= V
26
6
6
6
DD
DDR3-1066
/ 2.
1.875
7-7-7
160
187
27
20
20
27
48
59
86
7
7
7
4
6
DD
8-8-8
28
8
8
8
balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in
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7-7-7
31
7
7
7
8-8-8
32
8
8
8
DDR3-1333
107
200
234
1.5
24
20
30
60
74
4
5
9-9-9
33
9
9
9
10-10-10
10
10
34
10
DDP 2Gb DDR3 SDRAM
DDQ
8-8-8
36
8
8
8
balls of the DDR3 SDRAM under test tied
9-9-9
37
9
9
9
DDR3-1600
Rev. 1.0 March 2009
1.25
10-10-10
128
240
280
28
24
32
72
88
5
6
10
10
38
10
11-11-11
DD
11
11
39
11
and V
Unit
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
DDQ
ns