cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 232
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cn8237
Manufacturer Part Number
cn8237
Description
Atm Oc-12 Servicesar Plus With Xbr Traffic Management
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8237.pdf
(415 pages)
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8.0 DMA Coprocessor
8.6 Control Bit by Bit Endian Transfers
8.6.4 Master Data Dword Swap
Figure 8-4. Master Data Dword Swap—64-bit Transfer
8-6
Host Address[2:0] = 000
Host Address[2:0] = 001
Host Address[2:0] = 011
Host Address[2:0] = 010
11 10 9 8
10 9
0
8
1
9
3 2
2 1
Assumes PCI Address
Space is Nonstandard
15
7
0
8
15
14
ATM Cell
1 0
0
8 7
6
7
15
13
14
6
5
Special Status bit 27 control swaps 32-bit words in 64-bit transaction of host
writing data to host buffers and reading host buffers from host buffers. Bit 15
(ENDIAN) in SRC Configuration Register 0 is 0. See
13
15
14
12
5
7 6
6 5
4 3 2 1
14
13
11
12
4
0
13 12
12 11
11 10
10 9
3
5 4
4 3
1 2
Mindspeed Technologies
2
(decimal)
(decimal)
(decimal)
(decimal)
3 4
Addr
Addr
Addr
Addr
16
16
00
08
00
08
00
08
16
00
08
5 6 7
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
8 9 10 11 12 13 14 15
PCI Host Address Space Length
Host Address[2:0] = 101
Host Address[2:0] = 110
Host Address[2:0] = 100
Host Address[2:0] = 111
(Number of 64-bit words) = 2
14
13
12
15
6
5
7
4
13
12
11
14
5
4
6
3
12
11
13 12
10
4
3
™
5
2
10
11
3
2
9
4
1
16
11
10
2
1
0
9
8
3
15
10
8
1
9
0
2
7
15 14
14
7
8 7
0
1
6 5
9 8
Figure 8-4
15
13
0
6
(decimal)
(decimal)
(decimal)
(decimal)
Addr
Addr
Addr
Addr
16
00
08
16
16
00
08
00
08
16
00
08
28237-DSH-001-C
and
Figure
CN8237
8237_145
8-5.
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