cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 262

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

12.0 PCI Bus Interface
12.1 Overview
12-2
NOTE:
The PCI bus interface functional blocks are as follows:
• I/O drivers and receivers that drive the pins connected to the PCI bus
• PCI bus master logic that allows the bus interface to acquire mastership of
• Burst FIFO buffers that store and transfer bursts of data words between the
• PCI bus slave logic that responds to transactions initiated by other masters
• Configuration registers holding initialization parameters and PCI bus
• Logic that allows the host CPU to read/write the internal CN8237 registers
• Logic to enable read/write access to the SAR-shared memory space from
• An Interface module that allows the PCI core to connect to a serial
• Implement Sections 3.1.8 and Section 7.2 of the Compact PCI Hot Swap
signals.
the PCI bus and act as a transaction initiator. The bus master logic also
contains a command decoder that interprets access commands generated
by the DMA coprocessor, and a burst controller for controlling the
duration of each read or write burst. In addition, the bus master logic
contains address counters that allow it to restart and retry burst transfers if
required by the transaction target.
DMA coprocessor and the PCI bus master logic.
on the PCI bus with the CN8237 as a target. The bus slave logic also
synchronizes data passed back and forth across the clock boundary
between the PCI bus interface and the internal chip logic.
status information.
via the PCI slave port.
the host CPU, again via the PCI slave port.
EEPROM.
Specification. Assume that a logic low on the HSWITCH* input is switch
locked and a logic high is switch unlocked. The HSWITCH* input to the
SAR is asynchronous and may cause the state machine to transition to the
wrong state. Use the PCI clock to latch HSWITCH* and then provide the
latched signal to the SAR. Put PCI Reset on the flip flop to clear the latch
on power up.
The arming/disarming of the INS/EXT bits provides a switch debounce
function.
If HSWITCH* is not used, it must be tied to ground.
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
28237-DSH-001-C
CN8237