cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 266

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

12.0 PCI Bus Interface
12.5 Burst FIFO Buffers
12-6
NOTE:
12.5 Burst FIFO Buffers
Two small FIFO buffers are implemented to support PCI slave burst-mode
operation (Read = 8 × 32, Write = 64 × 32), to allow synchronization between the
CN8237 internal logic and the PCI bus interface, and to carry commands from the
DMA coprocessor to the PCI bus logic. The incoming master FIFO is 512 × 32 or
2 K × 32 bits, the outgoing Master FIFO is 16 × 36 bits.
12.6 PCI Bus Slave Logic
The PCI slave logic permits the host CPU on the PCI bus to access and modify
CN8237 resources (the external SAR-shared memory, internal memory, and
internal registers). Because the control processor also has access to these
resources, the PCI slave logic must arbitrate for access prior to performing any
read or write transaction. The slave logic also contains the PCI configuration
registers. These registers control the PCI slave and master interfaces, and can be
read or written at any time by the PCI host. The slave logic implements the
synchronizers required for rate-matching between the PCI bus clock and the
internal CN8237 system clock. Also, small FIFOs are used to speed up burst
reads and writes performed by the host processor to local resources, by buffering
prefetched read data and absorbing latency during consecutive writes.
target, responding to Memory Read, Memory Write, Configuration Read, and
Configuration Write commands from any initiator on the PCI bus. The slave
interface responds only to Memory Read and Memory Write commands if the
MS_EN bit of the Command field in the PCI Configuration register has been set.
to special cycles on the PCI bus. If a master performs a special cycle on the PCI
bus, the following occurs:
In general, the PCI slave interface functions as a normal memory-mapped PCI
The PCI slave logic does not implement special cycle commands, or respond
• The slave logic never asserts HDEVSEL*.
• Parity errors during the address phase of the special cycle command are
• Parity errors during the data phase are ignored.
block are under the control of PCI_READ_MULTI bit 22 in the CONFIG0
register.
If all targets are 64 bit, then the SAR can be programmed to master 64-bit
transactions only. This results in a modest performance increase. This is
programmable with the FORCE64 (bit 14 in CONFIG0).
reported to be asserting HSERR* in the normal fashion, if SE_EN and
PE_EN in the command register are both set.
Mindspeed Technologies
The PCI Read and PCI Read MULTIPLE commands issued by the PCI
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
28237-DSH-001-C
CN8237