cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 44

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.2 High Performance Host Architecture with Buffer Isolation
2.2.5 Write-only Control/Status
Figure 2-8. Write-only Control and Status Architecture
2-10
Host
Figure 2-8
manages the CN8237 ATM terminal using write-only control and status queues.
This architecture minimizes PCI bus utilization by eliminating reads from control
activities. PCI writes utilize the bus much more efficiently than PCI reads. During
a PCI write, the Bus Master can post the write data to an internal FIFO buffer in
the slave, terminate the transaction, and immediately release the bus. On the other
hand, during PCI reads, the Bus Master retrieves the data from the slave while
holding the bus. Since the data retrieval takes some time, reads increase the PCI
bus utilization time for each transaction. The CN8237 eliminates read operations
except for burst reads to gather segmentation data.
Write-only architecture reduces PCI utilization dramatically,
Mindspeed Technologies
as reads take many more clock cycles.
illustrates the CN8237’s write-only PCI control architecture. The host
SEG Data (Read Multiples)
RSM Data (Writes)
Control
Status
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
PCI
™
CN8237
28237-DSH-001-C
CN8237
8237_021