cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 253

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

28237-DSH-001-C
11.0 PHY Interface
11.1 Overview
A physical microprocessor interface provides access to the microprocessor port of
one physical device directly through the PCI interface. The interface consists of
dedicated control signals and address/data signals. The PHY interface directly
decodes accesses from the slave interface without using local memory bus
bandwidth.
SYSCLK) is provided. Also, each eight byte access across the PCI bus to the
PHY memory mapped space accesses one byte from the PHY device. To allow for
256 bytes of PHY control and status space 0x800 bytes of PCI memory map
space is reserved for PHY access.
DWORD is ignored. In addition, burst reads into PHY space cause a disconnect
after the first quad word is transferred. If a burst read is performed, the bridge
chip performs a retry with the address incremented. In PCI lite mode, dummy
words are inserted after the first valid transfer of a burst.
mechanism. This allows address bit to be appended to PHY control access
without increasing the size of the PHY memory map as seen by the PCI. The
PHYBANK field in the CONFIG1 control register provides up to 5 bits of page
addressing for a total of 13 bits of PHY addressing.
11.2 Microprocessor Interface to PHY Device(s)
Microprocessor interface pins and descriptions are given in
Figure 11-1
ATM receiver/transmitter device. The PCS*, PAS*, and PWNR pins are outputs
providing chip select, address strobe, and write/read control to the RS825x.
PINT* is an input connected to the interrupt sources of the RS825x. The PDS*
output is active and indicates the cycles in which the data transaction occurs. The
PWAIT* input is active and can be used to prolong the cycle as shown in
Figure
Each 64-bit PCI access generates only one access to the PHY. The upper
Multi-PHY or extended addressing for a PHY is provided through a PHY page
A PHY clock that runs up to 33 MHz (the PHY clock is a divide by 2 of
11-2. Physical interface devices other than Mindspeed PHY devices, such
Mindspeed Technologies
shows the signal interface between the CN8237 and the RS825x
11
™
Table
11-1.
11-1