cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 3

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

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Multi-Queue Segmentation Processing
The CN8237’s segmentation coprocessor generates ATM cells for up to 64 K VCCs at a line rate of up to 600 Mbps for
simplex connections. The segmentation coprocessor formats cells on each channel according to segmentation VCC
tables, utilizing up to 32 independent transmit queues and reporting segmentation status on a parallel set of up to 32
segmentation status queues. The segmentation coprocessor gathers client data from the host, formats ATM cells while
generating and appending protocol overhead, and forwards these to the UTOPIA port. The segmentation coprocessor
operates as a slave to the xBR Traffic Manager which schedules VCCs for transmission.
Multi-Queue Reassembly Processing
The CN8237’s reassembly coprocessor stores the payload data from the cell stream received by the UTOPIA port into
host data buffers. Using a dynamic lookup method which supports NNI or UNI addressing, the reassembly coprocessor
processes up to 64 K VCCs simultaneously at a line rate up to 600 Mbps. The host supplies free buffers on up to 32
independent free buffer queues. The reassembly coprocessor performs all CPCS protocol checks and reports the
results of these checks and other status data on one of 32 independent reassembly status queues.
High Performance Host Architecture with Buffer Isolation
The CN8237 host interface architecture maximizes performance and system flexibility. The device’s control and status
queues enable host/SAR communication via write operations alone. This “write only” architecture lowers latency and
PCI bus occupancy. Flexibility is achieved by supporting a scalable peer-to-peer architecture. Multiple host clients can
be addressed by the segmentation and reassembly (SAR) as separate physical or logical PCI peers. Segmentation and
reassembly data buffers on the host system are identified by buffer descriptors in SAR-local (or host) memory which
contain pointers to buffers. The use of buffer descriptors in this way allows isolation of data buffers from the
mechanisms that handle buffer allocation and linking. This provides a layer of indirection in buffer assignment and
management that maximizes system architecture flexibility.
Designer Toolkit
Mindspeed supplies a toolkit designers can use to establish an evaluation environment for the CN8237. The toolkit,
(CN8237EVM) includes a working reference design, an example of a software driver, and facilities for generating and
terminating all service categories of ATM traffic. In addition, because the CN8237 buffer management and control
architecture is based on Mindspeed’s 155 Mbps ServiceSAR family (Bt8233, RS8234, RS8235, and CN8236), it allows
for straight-forward migration of preexisting software. Together the toolkit and architecture enable rapid prototyping
and accelerate ATM system development.
28237-DSH-001-C
The PCI bus is the management, control and data plane for the CN8237 SAR. In order for the CN8237 SAR to achieve
OC-12 line rate, the PCI bus performance MUST be optimized to the maximum extent by ensuring the following:
Important System Performance Requirements:
1) There can be NO retries issued by the target slave device when the SAR is requesting a read transaction for
3) Refer to the Mindspeed web site for additional performance related material
2) The PCI bus arbiter should implement the following signaling protocols:
packet segmentation. The address to data latency [PCI 2.2 Specification section 3.5.1.1] for a SAR
segmentation read MUST be 9 PCI clock cycles or less. All subsequent word transfers should require one clock
cycle each.
a) the arbiter should "park" the bus with the SAR [PCI 2.2 Spec. section 3.4.3]
b) one GNT# may be deasserted coincident with another GNT# being asserted if the bus is not in the Idle
state.
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