cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 57

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
28237-DSH-001-C
SAR Shared Memory I/O (SEG and RSM)
To simplify system implementations, the CN8237 integrates two complete
memory controllers designed for direct interface to either ZBT or syncburst
synchronous SRAM. There are two CN8237 memory controllers: one for
reassembly and one for segmentation. They operates up to 66 MHz and each
controller can access up to 4 MB of either ZBT or syncburst synchronous SRAM
memory. The memory controller also arbitrates access to the internal control and
status registers by the host processor. The memory banks can be configured to a
variable number of sizes. All of this affords a wide degree of flexibility in
SAR-shared memory architecture.
Physical Layer Device Microprocessor I/O
A physical microprocessor interface provides access to the microprocessor port of
one physical device directly through the PCI interface. The interface consists of
dedicated control signals and address/data signals. The PHY interface directly
decodes accesses from the slave interface without using local memory bus
bandwidth.
Boundary Scan I/O and Loopbacks
The CN8237 includes five pins for Joint Test Action Group (JTAG) Boundary
Scan, for board-level testing. The CN8237 incorporates an internal loopback
from the segmentation coprocessor to the reassembly coprocessor, to facilitate
system diagnostics.
2.9 Electrical/Mechanical
The CN8237 is a CMOS device packaged in a 456 Ball Gate Array (BGA)
format. It operates from a 3.3 V power supply and within the standard industrial
temperature range.
be used. Any I/O (except PCI) requiring a pullup must be tied through a resistor
to 3.3 V.
2.10 Logic Diagram and Pin Descriptions
A functionally partitioned logic diagram of the CN8237 is illustrated in
Figure
Table
The device inputs are tolerant of 5 V signal levels, so external 5 V devices can
2-1.
2-11. Pin descriptions, names, and input/output assignments are detailed in
Mindspeed Technologies
™
2.0 Architecture Overview
2.9 Electrical/Mechanical
2-23