cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 250

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

10.0 Local Memory Interface
10.3 Memory Size Analysis
Figure 10-1. ZBT or Syncburst Synchronous SRAM Bank Utilizing By_16 Devices
10-4
Synchronous
256 k x 16
Syncburst
ZBT or
SRAM
D[15:0]
A[17:0]
BWa*
BWb*
R/W*
CLK
CE*
D[15:0]
Synchronous
256 k x 16
Syncburst
ZBT or
SRAM
device).
that the memory controller uses to access the ZBT or syncburst synchronous
SRAM. A logic 0 indicates 0 wait state or single-cycle memory, while a logic 1
indicates one wait state or two-cycle memory. The power-on default is
MEMCTRL=1, selecting one wait state or two-cycle memory accesses.
interface are always 0 wait state. When the CN8237 decodes a PCI slave read to
its address space, the CN8237 performs a prefetch of four subsequent
(contiguous) word locations.
proportional to the system clock speed, as well as the amount and organization of
the memory. The required system clock speed for a given application is dependent
on the physical line rate, number of VCCs, and the percentage of idle cells versus
assigned cells. The system designer can choose the appropriate ZBT or syncburst
synchronous SRAM characteristics to suit the amount of memory and
organization required for the application. See
information.
10.3 Memory Size Analysis
Table 10-4
the following assumptions:
D[15:0]
A[17:0]
BWa*
BWb*
R/W*
CLK
CE*
The memory map contains space allocated to the RS825x (physical layer
The MEMCTRL bit in the CONFIG0 register selects the number of wait states
The internal register and internal memory accesses from the PCI slave
ZBT or syncburst synchronous SRAM access time requirements are directly
SEGMENTATION
1.
The Schedule table is 8,448 schedule slots and each slot is a double word.
This allows CBR and three-priority VBR schedule in 64 Kbps increments
for an OC-12 connection.
D[31:16]
Mindspeed Technologies
lists the memory size requirements for 1,024 configured VCCs under
SADDR[17:0]
SDATA[31:0]
SCSx*
SBW[0]*
SBW[1]*
SBW[2]*
SBW[3]*
SRNW*
SCLK[0]*
CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
RADDR[17:0]
RDATA[31:0]
RCLK[0]*
RBW[0]*
RBW[1]*
RBW[2]*
RBW[3]*
RRNW*
RCSx*
D[31:16]
™
Synchronous
A[17:0]
D[15:0]
CE*
BWa*
BWb*
R/W*
CLK
256 k x 16
Syncburst
Chapter 16.0
ZBT or
SRAM
D[15:0]
for timing
28237-DSH-001-C
Synchronous
A[17:0]
D[15:0]
CE*
BWa*
BWb*
R/W*
CLK
256 k x 16
Syncburst
ZBT or
SRAM
CN8237
8237_083