ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 105

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272M
21.3.2
21.3.3
21.3.4
Table 44.
Mode
Idle
Exiting stand-by mode
After the system has entered the Stand-by mode, the procedure to exit this mode consists of
a standard Power-on sequence, with the only difference that the RAM is already powered
through V
It is recommended to held the device under RESET (RSTIN pin forced low) until external
V
device is maintained under reset by the internal low voltage detector circuit (implemented
inside the main voltage regulator) till the internal V
is no guaranty that the device stays under reset status if RSTIN is at high level during
power ramp up. So, it is important the external hardware is able to guarantee a stable
ground level on RSTIN along the power-on phase, without any temporary glitch.
The external hardware is responsible for driving the RSTIN pin low until the V
even though the internal LVD is active.
Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to
the main V
At this time, everything becomes stable, and the execution of the initialization routines can
start: XRAM2EN bit can be set, enabling the RAM.
Real time clock and stand-by mode
When Stand-by mode is entered (turning off the main supply V
counting can be maintained running in case the on-chip 32 kHz oscillator is used to provide
the reference to the counter. This is not possible if the main oscillator is used as reference
for the counter: Being the main oscillator powered by V
oscillator is stopped.
Power reduction modes summary
The different Power reduction modes are summarized in the following
Power reduction modes summary
DD
on
on
voltage pin is stable. Even though, at the very beginning of the power-on phase, the
Warning:
18SB
18
.
on
on
internal reference (derived from V
During power-off phase, it is important that the external
hardware maintains a stable ground level on RSTIN pin,
without any glitch, in order to avoid spurious exiting from
reset status with unstable power supply.
off
off
on
on
off
on
STBY
18
becomes higher than about 1.0V, there
pin external voltage).
run
run
DD
, once this is switched off, the
DD
off
on
), the Real Time Clock
Power reduction modes
Table
biased
biased
44.
DD
is stable,
biased
biased
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