ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 169

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ST10F272M-4Q3

Manufacturer Part Number
ST10F272M-4Q3
Description
16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
ST10F272M
Figure 62. SSC slave timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
2. The bit timing is repeated for all bits to be transmitted or received.
SCLK
MRST
MTSR
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
(1)
t
315
t
1st in bit
317
1st out bit
t
310
t
318
t
t
314
315
t
311
2nd out bit
2nd in bit
t
312
t
t
316
313
(2)
t
315
Last in bit
t
317
Electrical characteristics
Last out bit
t
318
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