ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 166

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics
24.8.20
24.8.20.1 Master mode
Table 74.
166/176
t
t
t
t
t
t
t
Symbol
300
301
302
303
304
305
306
CC SSC clock cycle time
CC SSC clock high time
CC SSC clock low time
CC SSC clock rise time
CC SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge
Figure 60. External bus arbitration (regaining the bus)
1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated
2. The next ST10F272M driven bus cycle may start here.
High-speed synchronous serial interface (SSC) timing
V
SSC master mode timings
DD
earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be
deactivated without the ST10F272M requesting the bus.
= 5V ±10%, V
CSx
(On P6.x)
Other
signals
CLKOUT
Parameter
BREQ
HOLD
HLDA
(2)
SS
= 0V, T
(3)
t
62
A
= -40 to +125°C, C
(<SSCBR> = 0002h)
Maximum baudrate
Min
t
150
63
63
61
@ f
-2
–
–
–
6.6 Mbaud
CPU
(1)
t
62
= 40 MHz
t
62
(1)
Max
150
L
10
10
15
–
–
–
= 50pF
t
t
63
67
(2)
(<SSCBR> = 0001h - FFFFh)
t
65
t
t
300
300
8TCL
Min
Variable baudrate
/ 2 - 12
/ 2 - 12
-2
–
–
–
262144 TCL
Max
10
10
15
–
–
–
ST10F272M
Unit
ns
ns
ns
ns
ns
ns
ns