ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 145

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272M
Table 62.
1. The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is 64 to 128 MHz. The CPU clock
24.8.9
0
0
0
(P0H.7-5)
P0.15-13
frequency range when PLL is used is 16 to 40 MHz.
1
0
0
0
1
0
Internal PLL divider mechanism (continued)
Example 1
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Example 2
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PLL jitter
The following terminology is hereafter defined:
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Jitter at the PLL output can be due to the following reasons:
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XTAL frequency
4 to 8 MHz
f
P0(15:13) = ‘110’ (multiplication by 3)
PLL input frequency = 1 MHz
VCO frequency = 48 MHz: NOT VALID, must be 64 to 128 MHz
f
f
P0(15:13) = ‘100’ (multiplication by 5)
PLL input frequency = 2 MHz
VCO frequency = 80 MHz
PLL output frequency = 40 MHz (VCO frequency divided by 2)
f
Self referred single period jitter
Also called “Period Jitter”, it can be defined as the difference of the T
where T
time period of the PLL output clock.
Self referred long term jitter
Also called “N period jitter”, it can be defined as the difference of T
T
minimum time difference between N+1 clock rising edges. Here N should be kept
sufficiently large to have the long term jitter. For N=1, this becomes the single period
jitter.
Jitter in the input clock
Noise in the PLL loop
XTAL
CPU
XTAL
CPU
max
4 MHz
= NOT VALID
= 40 MHz (no effect of Output Prescaler)
is the maximum time difference between N+1 clock rising edges and T
= 4 MHz
= 8 MHz
max
(1)
is maximum time period of the PLL output clock and T
prescaler
f
XTAL
Input
–
/ 2
Multiply by
40
PLL bypassed
PLL
–
Divide by
2
prescaler
Output
f
PLL
–
Electrical characteristics
/ 2
max
min
max
CPU frequency
f
is the minimum
and T
CPU
f
and T
XTAL
f
XTAL
= f
min
min
XTAL
x 10
/ 2
min
, where
is the
145/176
x F
,