ST10F272M-4Q3 STMICROELECTRONICS [STMicroelectronics], ST10F272M-4Q3 Datasheet - Page 137

• Manufacturer Part Number: ST10F272M-4Q3
• Description: 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST10F272M
(sampled voltage on C
must be designed to respect the following relation:
The formula above provides constraints for external network design, in particular on
resistive path.
A second aspect involving the capacitance network must be considered. Assuming the three
capacitances C
equivalent circuit shown in
close), a charge sharing phenomena is installed.
Figure 41. Charge sharing timing diagram during sampling phase
In particular two different transient periods can be distinguished (see
●
A first and quick charge transfer from the internal capacitance C
sampling capacitance C
considering a worst case (since the time constant in reality would be faster) in which
C
are in series, and the time constant is:
This relation can again be simplified considering only C
condition. In reality, the transient is faster, but the A/D Converter circuitry has been
designed to be robust also in the very worst case: the sampling time T
longer than the internal time constant:
The charge of C
voltage V
P2
V
is shown in parallel to C
V
V
V
CS
A
A2
A1
A1
1
F
, C
on the capacitance according to the following equation:
P1
Voltage Transient on C
P1
and C
S
) and the sum of R
and C
V A1
V A
Figure
2
τ 1
P2
S
⋅
⋅
<
P2
(
R S
----------------------------------------------------------------------------- -
initially charged at the source voltage V
occurs (C
C S
(
τ 1
R SW
is redistributed also on C
P1
+
40), when the sampling phase is started (A/D switch
+
=
R F
(call C
C P1
(
R SW
+
+
R AD
S
R L
+
S
R EQ
is supposed initially completely discharged):
C P2
P
S
+
+
T
= C
+ R
)
R AD
S
R SW
⋅
C S
)
P1
F
=
∆V < 0.5 LSB
t
)
+ R
< <
⋅
V A
+ C
+
---------------------- -
C P
C P C S
R AD
L
⋅
P2
T
+
(
+ R
⋅
C P1
S
), the two capacitance C
C S
τ
τ
<
1
2
S
SW
, determining a new value of the
< (R
= R
1
-- - LSB
2
S
+
+ R
as an additional worst
C P2
L
SW
(C
Electrical characteristics
AD
S
+ R
)
+ C
, the external circuit
P1
Figure
AD
A
P1
and C
(refer to the
) C
+ C
S
S
is always much
<< T
41):
P2
P2
)
S
to the
P
and C
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S